AGESA F15 wrapper for Trinity
The wrapper for Trinity. Support S3. Parme is a example board. Change-Id: Ib4f653b7562694177683e1e1ffdb27ea176aeaab Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1156 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
zbao
Patrick Georgi
parent
7d94cf93ee
commit
2c08f6ade4
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@ -237,7 +237,7 @@ struct lb_memory *write_tables(void)
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* the result right now. If it fails, ACPI resume will be disabled.
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*/
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cbmem_add(CBMEM_ID_RESUME, HIGH_MEMORY_SAVE);
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#if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14
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#if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
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cbmem_add(CBMEM_ID_RESUME_SCRATCH, CONFIG_HIGH_SCRATCH_MEMORY_SIZE);
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#endif
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#endif
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@ -23,6 +23,7 @@ config CPU_AMD_AGESA
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default y if CPU_AMD_AGESA_FAMILY12
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default y if CPU_AMD_AGESA_FAMILY14
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default y if CPU_AMD_AGESA_FAMILY15
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default y if CPU_AMD_AGESA_FAMILY15_TN
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default n
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if CPU_AMD_AGESA
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@ -42,6 +43,6 @@ source src/cpu/amd/agesa/family10/Kconfig
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source src/cpu/amd/agesa/family12/Kconfig
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source src/cpu/amd/agesa/family14/Kconfig
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source src/cpu/amd/agesa/family15/Kconfig
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source src/cpu/amd/agesa/family15tn/Kconfig
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endif # CPU_AMD_AGESA
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@ -20,6 +20,7 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY10) += family10
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subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += family12
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subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += family14
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subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15) += family15
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subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) += family15tn
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romstage-$(CONFIG_HAVE_ACPI_RESUME) += s3_resume.c
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ramstage-$(CONFIG_HAVE_ACPI_RESUME) += s3_resume.c
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@ -32,7 +32,7 @@
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#include <cpu/x86/mtrr.h>
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#include <cpu/amd/amdfam15.h>
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static msr_t rdmsr_amd(u32 index)
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msr_t rdmsr_amd(u32 index)
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{
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msr_t result;
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__asm__ __volatile__(
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@ -43,7 +43,7 @@ static msr_t rdmsr_amd(u32 index)
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return result;
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}
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static void wrmsr_amd(u32 index, msr_t msr)
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void wrmsr_amd(u32 index, msr_t msr)
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{
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__asm__ __volatile__(
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"wrmsr"
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@ -0,0 +1,79 @@
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#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2012 Advanced Micro Devices, Inc.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#
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config CPU_AMD_AGESA_FAMILY15_TN
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bool
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select PCI_IO_CFG_EXT
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config CPU_ADDR_BITS
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int
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default 36
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depends on CPU_AMD_AGESA_FAMILY15_TN
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config CPU_SOCKET_TYPE
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hex
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default 0x10
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depends on CPU_AMD_AGESA_FAMILY15_TN
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# DDR2 and REG
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config DIMM_SUPPORT
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hex
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default 0x0104
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depends on CPU_AMD_AGESA_FAMILY15_TN
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config EXT_RT_TBL_SUPPORT
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bool
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default n
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depends on CPU_AMD_AGESA_FAMILY15_TN
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config EXT_CONF_SUPPORT
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bool
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default n
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depends on CPU_AMD_AGESA_FAMILY15_TN
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config CBB
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hex
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default 0x0
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depends on CPU_AMD_AGESA_FAMILY15_TN
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config CDB
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hex
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default 0x18
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depends on CPU_AMD_AGESA_FAMILY15_TN
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config XIP_ROM_BASE
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hex
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default 0xfff80000
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depends on CPU_AMD_AGESA_FAMILY15_TN
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config XIP_ROM_SIZE
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hex
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default 0x100000
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depends on CPU_AMD_AGESA_FAMILY15_TN
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config HAVE_INIT_TIMER
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bool
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default y
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depends on CPU_AMD_AGESA_FAMILY15_TN
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config HIGH_SCRATCH_MEMORY_SIZE
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hex
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# Assume the maximum size of stack as (0xA0000 - 0x30000 + 0x1000)
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default 0xA1000
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depends on CPU_AMD_AGESA_FAMILY15_TN
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@ -0,0 +1,466 @@
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#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2012 Advanced Micro Devices, Inc.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#
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ramstage-y += chip_name.c
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driver-y += model_15_init.c
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AGESA_ROOT = ../../../../vendorcode/amd/agesa/f15tn
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agesa_lib_src =
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agesa_lib_src += $(AGESA_ROOT)/Legacy/Proc/Dispatcher.c
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agesa_lib_src += $(AGESA_ROOT)/Legacy/Proc/agesaCallouts.c
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agesa_lib_src += $(AGESA_ROOT)/Legacy/Proc/hobTransfer.c
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agesa_lib_src += $(AGESA_ROOT)/Lib/amdlib.c
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agesa_lib_src += $(AGESA_ROOT)/Lib/helper.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnC6State.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnCpb.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnEquivalenceTable.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnInitEarlyTable.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnIoCstate.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnLogicalIdTables.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600110F_Enc.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatchTables.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnMsrTables.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnPciTables.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnPowerMgmtSystemTables.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnPowerPlane.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnSharedMsrTable.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnUtilities.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/cpuF15TnCacheFlushOnHalt.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/cpuF15TnCoreAfterReset.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/cpuF15TnDmi.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/cpuF15TnHtc.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/cpuF15TnNbAfterReset.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/cpuF15TnPowerCheck.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/cpuF15TnPsi.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/cpuF15TnPstate.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuCommonF15Utilities.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuF15BrandId.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuF15CacheDefaults.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuF15Dmi.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuF15MmioMap.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuF15MsrTables.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuF15PciTables.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuF15PowerCheck.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuF15Utilities.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuF15WheaInitDataTables.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/PreserveMailbox.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuC6State.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCacheFlushOnHalt.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCacheInit.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCoreLeveling.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCpb.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuDmi.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuFeatureLeveling.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuFeatures.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuHtc.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuHwC1e.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuIoCstate.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuPsi.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuPstateGather.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuPstateLeveling.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuPstateTables.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuSlit.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuSrat.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuWhea.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/S3.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Table.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cahalt.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cahaltasm.S
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuApicUtilities.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuBist.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuBrandId.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuEarlyInit.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuEventLog.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuFamilyTranslation.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuGeneralServices.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuInitEarlyTable.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuLateInit.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuMicrocodePatch.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuPostInit.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuPowerMgmt.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuPowerMgmtMultiSocket.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuPowerMgmtSingleSocket.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuWarmReset.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/heapManager.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitEarly.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitEnv.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitLate.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitMid.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitPost.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitReset.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitResume.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdLateRunApTask.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdS3LateRestore.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdS3Save.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/Common/CommonInits.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/Common/CommonReturns.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/Common/CreateStruct.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/Common/S3RestoreState.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/Common/S3SaveState.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Common/GnbLibFeatures.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtEarly.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtEnv.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtLate.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtMid.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtPost.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtReset.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtS3Save.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Library/GnbTimerLibWrap0/GnbTimerLibWrap0.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLib.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbFamTranslation/GnbTranslation.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxConfig/GfxConfigMid.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GfxEnvInitTN.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GfxIntegratedInfoTableTN.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GfxLibTN.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GfxMidInitTN.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GfxPostInitTN.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GfxTablesTN.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GnbBapmCoeffCalcTN.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GnbEarlyInitTN.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GnbEnvInitTN.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GnbIommuIvrsTN.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GnbMidInitTN.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GnbPostInitTN.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GnbTablesTN.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFS1.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PcieConfigTN.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PcieEarlyInitTN.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PcieEnvInitTN.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PcieLibTN.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PcieMidInitTN.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PciePostInitTN.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PciePowerGateTN.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PcieTablesTN.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbMSocketLib/GnbMSocketLib.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieAspm/PcieAspm.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV4/PcieMaxPayloadV4.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV4/PciePortServicesV4.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV4/PciePowerMgmtV4.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV4/PcieWrapperServicesV4.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbSbIommuLib/GnbSbIommuLib.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbSbLib/GnbSbLib.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbSview/GnbSview.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbTable/GnbTable.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Fam15Mod1x/htNbFam15Mod1x.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Fam15Mod1x/htNbUtilitiesFam15Mod1x.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htFeat.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htInterface.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htInterfaceCoherent.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htInterfaceGeneral.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htInterfaceNonCoherent.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htMain.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htNb.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htNotify.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/IDS/Control/IdsCtrl.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/IDS/Debug/IdsDebug.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/IDS/Debug/IdsDebugPrint.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/IDS/Debug/IdsDpSerial.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/IDS/Family/0x15/TN/IdsF15TnAllService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/IDS/Library/IdsLib.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ardk/ma.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/CHINTLV/mfchi.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/CSINTLV/mfcsi.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/DMI/mfDMI.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/ECC/mfecc.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/ECC/mfemp.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/IDENDIMM/mfidendimm.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/INTLVRN/mfintlvrn.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/LVDDR3/mflvddr3.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/MEMCLR/mfmemclr.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/PARTRN/mfParallelTraining.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/PARTRN/mfStandardTraining.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/S3/mfs3.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/TABLE/mftds.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/TN/mmflowtn.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mdef.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/merrhdl.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/minit.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mm.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmConditionalPso.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmEcc.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmExcludeDimm.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmLvDdr3.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmMemClr.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmMemRestore.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmNodeInterleave.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmOnlineSpare.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmParallelTraining.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmStandardTraining.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmUmaAlloc.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmflow.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mu.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/muc.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/TN/mndcttn.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/TN/mnflowtn.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/TN/mnidendimmtn.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/TN/mnmcttn.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/TN/mnottn.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/TN/mnphytn.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/TN/mnregtn.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/TN/mns3tn.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/TN/mntn.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mn.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnS3.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mndct.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnfeat.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnflow.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnmct.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnphy.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnreg.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mntrain3.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/TN/FM2/mpUtnfm2.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/TN/FP2/mpStnfp2.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/TN/FS1/mpStnfs1.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/TN/mpStn3.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/TN/mpUtn3.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/TN/mptn3.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/mp.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/mpmaxfreq.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/mpmr0.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/mpodtpat.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/mprtt.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/mpsao.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mt3.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtot3.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtrci3.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtsdi3.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtspd3.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mttecc3.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mttwl3.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mt.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mthdi.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttEdgeDetect.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttdimbt.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttecc.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mtthrc.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mtthrcSeedTrain.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttml.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttoptsrc.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttsrc.c
|
||||
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Azalia/AzaliaEnv.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Azalia/AzaliaLate.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Azalia/AzaliaMid.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Azalia/AzaliaReset.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Common/AcpiLib.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Common/FchCommon.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Common/FchLib.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Common/FchPeLib.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Common/MemLib.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Common/PciLib.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Gec/Family/Hudson2/Hudson2GecEnvService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Gec/Family/Hudson2/Hudson2GecService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Gec/GecEnv.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Gec/GecLate.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Gec/GecMid.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Gec/GecReset.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiEnvService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiLateService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiMidService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2SSService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/HwAcpi/HwAcpiEnv.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/HwAcpi/HwAcpiLate.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/HwAcpi/HwAcpiMid.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/HwAcpi/HwAcpiReset.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmEnvService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmLateService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmMidService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Hwm/HwmEnv.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Hwm/HwmLate.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Hwm/HwmMid.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Hwm/HwmReset.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Ide/IdeEnv.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Ide/IdeLate.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Ide/IdeMid.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Imc/Family/Hudson2/Hudson2ImcService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Imc/FchEcEnv.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Imc/FchEcLate.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Imc/FchEcMid.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Imc/FchEcReset.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Imc/ImcEnv.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Imc/ImcLate.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Imc/ImcLib.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Imc/ImcMid.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Imc/ImcReset.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Interface/Family/Hudson2/EnvDefHudson2.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Interface/Family/Hudson2/ResetDefHudson2.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Interface/FchInitEnv.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Interface/FchInitLate.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Interface/FchInitMid.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Interface/FchInitReset.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Interface/FchInitS3.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Interface/FchTaskLauncher.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Interface/InitEnvDef.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Interface/InitResetDef.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Ir/IrEnv.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Ir/IrLate.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Ir/IrMid.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcib/PcibEnv.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcib/PcibLate.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcib/PcibMid.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcib/PcibReset.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/AbEnv.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/AbLate.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/AbMid.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/AbReset.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbEnvService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbResetService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppResetService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/Family/Hudson2/Hudson2PcieEnvService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/Family/Hudson2/Hudson2PcieService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/GppEnv.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/GppHp.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/GppLate.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/GppLib.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/GppMid.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/GppPortInit.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/GppReset.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/PcieEnv.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/PcieLate.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/PcieMid.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/PcieReset.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/AhciEnv.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/AhciLate.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/AhciLib.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/AhciMid.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/Family/Hudson2/Hudson2SataEnvService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/Family/Hudson2/Hudson2SataResetService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/Family/Hudson2/Hudson2SataService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/Ide2AhciEnv.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/Ide2AhciLate.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/Ide2AhciLib.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/Ide2AhciMid.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/RaidEnv.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/RaidLate.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/RaidLib.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/RaidMid.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataEnv.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataEnvLib.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataIdeEnv.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataIdeLate.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataIdeLib.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataIdeMid.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataLate.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataLib.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataMid.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataReset.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sd/Family/Hudson2/Hudson2SdEnvService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sd/Family/Hudson2/Hudson2SdResetService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sd/Family/Hudson2/Hudson2SdService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sd/SdEnv.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sd/SdLate.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sd/SdMid.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcEnvService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcResetService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Spi/LpcEnv.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Spi/LpcLate.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Spi/LpcMid.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Spi/LpcReset.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Spi/SpiEnv.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Spi/SpiLate.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Spi/SpiMid.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Spi/SpiReset.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/EhciEnv.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/EhciLate.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/EhciMid.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/EhciReset.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciEnvService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciLateService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciMidService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciEnvService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciLateService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciMidService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciEnvService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciLateService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciMidService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciResetService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/OhciEnv.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/OhciLate.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/OhciMid.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/OhciReset.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/UsbEnv.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/UsbLate.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/UsbMid.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/UsbReset.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/XhciEnv.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/XhciLate.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/XhciMid.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/XhciReset.c
|
||||
|
||||
|
||||
romstage-y += $(agesa_lib_src)
|
||||
ramstage-y += $(agesa_lib_src)
|
||||
|
||||
subdirs-y += ../../mtrr
|
||||
subdirs-y += ../../../x86/tsc
|
||||
subdirs-y += ../../../x86/lapic
|
||||
subdirs-y += ../../../x86/cache
|
||||
subdirs-y += ../../../x86/mtrr
|
||||
subdirs-y += ../../../x86/pae
|
||||
subdirs-y += ../../../x86/smm
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
extern struct chip_operations cpu_amd_agesa_family15tn_ops;
|
||||
|
||||
struct cpu_amd_agesa_family15tn_config {
|
||||
};
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <device/device.h>
|
||||
#include "chip.h"
|
||||
|
||||
struct chip_operations cpu_amd_agesa_family15tn_ops = {
|
||||
CHIP_NAME("AMD CPU Family 15h")
|
||||
};
|
||||
|
|
@ -0,0 +1,151 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cpu/amd/mtrr.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cpu/x86/pae.h>
|
||||
#include <pc80/mc146818rtc.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
|
||||
#include <cpu/cpu.h>
|
||||
#include <cpu/x86/cache.h>
|
||||
#include <cpu/x86/mtrr.h>
|
||||
#include <cpu/amd/amdfam15.h>
|
||||
#include <arch/acpi.h>
|
||||
#include <cpu/amd/agesa/s3_resume.h>
|
||||
|
||||
msr_t rdmsr_amd(u32 index)
|
||||
{
|
||||
msr_t result;
|
||||
__asm__ __volatile__(
|
||||
"rdmsr"
|
||||
:"=a"(result.lo), "=d"(result.hi)
|
||||
:"c"(index), "D"(0x9c5a203a)
|
||||
);
|
||||
return result;
|
||||
}
|
||||
|
||||
void wrmsr_amd(u32 index, msr_t msr)
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
"wrmsr"
|
||||
: /* No outputs */
|
||||
:"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a)
|
||||
);
|
||||
}
|
||||
|
||||
static void model_15_init(device_t dev)
|
||||
{
|
||||
printk(BIOS_DEBUG, "Model 15 Init.\n");
|
||||
|
||||
u8 i;
|
||||
msr_t msr;
|
||||
int msrno;
|
||||
#if CONFIG_LOGICAL_CPUS == 1
|
||||
u32 siblings;
|
||||
#endif
|
||||
|
||||
//x86_enable_cache();
|
||||
//amd_setup_mtrrs();
|
||||
//x86_mtrr_check();
|
||||
disable_cache ();
|
||||
/* Enable access to AMD RdDram and WrDram extension bits */
|
||||
msr = rdmsr(SYSCFG_MSR);
|
||||
msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
|
||||
msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn;
|
||||
wrmsr(SYSCFG_MSR, msr);
|
||||
|
||||
// BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs
|
||||
msr.lo = msr.hi = 0;
|
||||
wrmsr (0x259, msr);
|
||||
msr.lo = msr.hi = 0x1e1e1e1e;
|
||||
wrmsr(0x250, msr);
|
||||
wrmsr(0x258, msr);
|
||||
for (msrno = 0x268; msrno <= 0x26f; msrno++)
|
||||
wrmsr (msrno, msr);
|
||||
|
||||
msr = rdmsr(SYSCFG_MSR);
|
||||
msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
|
||||
msr.lo |= SYSCFG_MSR_MtrrFixDramEn;
|
||||
wrmsr(SYSCFG_MSR, msr);
|
||||
|
||||
#if CONFIG_HAVE_ACPI_RESUME == 1
|
||||
if (acpi_slp_type == 3)
|
||||
restore_mtrr();
|
||||
#endif
|
||||
|
||||
x86_mtrr_check();
|
||||
x86_enable_cache();
|
||||
|
||||
/* zero the machine check error status registers */
|
||||
msr.lo = 0;
|
||||
msr.hi = 0;
|
||||
for (i = 0; i < 6; i++) {
|
||||
wrmsr(MCI_STATUS + (i * 4), msr);
|
||||
}
|
||||
|
||||
|
||||
/* Enable the local cpu apics */
|
||||
setup_lapic();
|
||||
|
||||
#if CONFIG_LOGICAL_CPUS == 1
|
||||
siblings = cpuid_ecx(0x80000008) & 0xff;
|
||||
|
||||
if (siblings > 0) {
|
||||
msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
|
||||
msr.lo |= 1 << 28;
|
||||
wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
|
||||
|
||||
msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
|
||||
msr.hi |= 1 << (33 - 32);
|
||||
wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
|
||||
}
|
||||
printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
|
||||
#endif
|
||||
|
||||
/* DisableCf8ExtCfg */
|
||||
msr = rdmsr(NB_CFG_MSR);
|
||||
msr.hi &= ~(1 << (46 - 32));
|
||||
wrmsr(NB_CFG_MSR, msr);
|
||||
|
||||
|
||||
/* Write protect SMM space with SMMLOCK. */
|
||||
msr = rdmsr(HWCR_MSR);
|
||||
msr.lo |= (1 << 0);
|
||||
wrmsr(HWCR_MSR, msr);
|
||||
}
|
||||
|
||||
static struct device_operations cpu_dev_ops = {
|
||||
.init = model_15_init,
|
||||
};
|
||||
|
||||
static struct cpu_device_id cpu_table[] = {
|
||||
{ X86_VENDOR_AMD, 0x610f00 }, /* TN-A0 */
|
||||
{ 0, 0 },
|
||||
};
|
||||
|
||||
static const struct cpu_driver model_15 __cpu_driver = {
|
||||
.ops = &cpu_dev_ops,
|
||||
.id_table = cpu_table,
|
||||
};
|
||||
|
|
@ -225,6 +225,8 @@ void OemAgesaSaveMtrr(void)
|
|||
dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi);
|
||||
nvram_pos += 4;
|
||||
|
||||
write_spi_status((u8 *)spi_address, 0x3c);
|
||||
spi_write_disable((u8 *) spi_address);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
@ -273,6 +275,10 @@ u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data)
|
|||
S3_DATA_VOLATILE_POS + 0x2000);
|
||||
sector_erase_spi((u8 *) spi_address,
|
||||
S3_DATA_VOLATILE_POS + 0x3000);
|
||||
sector_erase_spi((u8 *) spi_address,
|
||||
S3_DATA_VOLATILE_POS + 0x4000);
|
||||
sector_erase_spi((u8 *) spi_address,
|
||||
S3_DATA_VOLATILE_POS + 0x5000);
|
||||
}
|
||||
|
||||
nvram_pos = 0;
|
||||
|
|
@ -283,6 +289,9 @@ u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data)
|
|||
dword_noneAAI_program((u8 *) spi_address, nvram_pos + pos + 4,
|
||||
*(u32 *) (Data + nvram_pos));
|
||||
}
|
||||
/* write_spi_status((u8 *)spi_address, 0x3c); */
|
||||
|
||||
/* spi_write_disable((u8 *) spi_address); */
|
||||
|
||||
return AGESA_SUCCESS;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -20,9 +20,9 @@
|
|||
#ifndef S3_RESUME_H
|
||||
#define S3_RESUME_H
|
||||
|
||||
#define S3_DATA_NONVOLATILE_POS 0xFFFF4000
|
||||
#define S3_DATA_NONVOLATILE_POS 0xFFFF7000
|
||||
#define S3_DATA_VOLATILE_POS 0xFFFF0000
|
||||
#define S3_DATA_MTRR_POS 0xFFFF3100
|
||||
#define S3_DATA_MTRR_POS 0xFFFF6000
|
||||
|
||||
typedef enum {
|
||||
S3DataTypeNonVolatile=0, ///< NonVolatile Data Type
|
||||
|
|
|
|||
|
|
@ -35,7 +35,16 @@
|
|||
#define CPU_ID_FEATURES_MSR 0xC0011004
|
||||
#define CPU_ID_EXT_FEATURES_MSR 0xC0011005
|
||||
|
||||
static msr_t rdmsr_amd(u32 index);
|
||||
static void wrmsr_amd(u32 index, msr_t msr);
|
||||
msr_t rdmsr_amd(u32 index);
|
||||
void wrmsr_amd(u32 index, msr_t msr);
|
||||
|
||||
#if defined(__PRE_RAM__)
|
||||
void wait_all_core0_started(void);
|
||||
void wait_all_other_cores_started(u32 bsp_apicid);
|
||||
void wait_all_aps_started(u32 bsp_apicid);
|
||||
void allow_all_aps_stop(u32 bsp_apicid);
|
||||
#endif
|
||||
u32 get_initial_apicid(void);
|
||||
void get_bus_conf(void);
|
||||
|
||||
#endif /* CPU_AMD_FAM15_H */
|
||||
|
|
|
|||
|
|
@ -285,6 +285,7 @@
|
|||
#define PCI_DEVICE_ID_ATI_RADEON_RD 0x5147
|
||||
|
||||
#define PCI_DEVICE_ID_AMD_15H_MODEL_000F_NB_HT 0x1600
|
||||
#define PCI_DEVICE_ID_AMD_15H_MODEL_001F_NB_HT 0x1400
|
||||
#define PCI_DEVICE_ID_AMD_10H_NB_HT 0x1200
|
||||
|
||||
#define PCI_DEVICE_ID_ATI_SB600_LPC 0x438D
|
||||
|
|
|
|||
|
|
@ -35,5 +35,6 @@ source src/northbridge/amd/agesa/family10/Kconfig
|
|||
source src/northbridge/amd/agesa/family12/Kconfig
|
||||
source src/northbridge/amd/agesa/family14/Kconfig
|
||||
source src/northbridge/amd/agesa/family15/Kconfig
|
||||
source src/northbridge/amd/agesa/family15tn/Kconfig
|
||||
|
||||
endif # NORTHBRIDGE_AMD_AGESA
|
||||
|
|
|
|||
|
|
@ -20,3 +20,4 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10) += family10
|
|||
subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY12) += family12
|
||||
subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14) += family14
|
||||
subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15) += family15
|
||||
subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN) += family15tn
|
||||
|
|
|
|||
|
|
@ -0,0 +1,42 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007-2009 coresystems GmbH
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
config NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
|
||||
bool
|
||||
select MMCONF_SUPPORT
|
||||
select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN_ROOT_COMPLEX
|
||||
|
||||
if NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
|
||||
|
||||
config HW_MEM_HOLE_SIZEK
|
||||
hex
|
||||
default 0x100000
|
||||
|
||||
config HW_MEM_HOLE_SIZE_AUTO_INC
|
||||
bool
|
||||
default n
|
||||
|
||||
config MMCONF_BASE_ADDRESS
|
||||
hex
|
||||
default 0xA0000000
|
||||
|
||||
config MMCONF_BUS_NUMBER
|
||||
int
|
||||
default 256
|
||||
|
||||
endif
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
#
|
||||
# This file is part of the coreboot project.
|
||||
#
|
||||
# Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; version 2 of the License.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
#
|
||||
|
||||
driver-y += northbridge.c
|
||||
|
|
@ -0,0 +1,302 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* No includes in this file because it is included into northbridge.c.
|
||||
*/
|
||||
|
||||
struct dram_base_mask_t {
|
||||
u32 base; //[47:27] at [28:8]
|
||||
u32 mask; //[47:27] at [28:8] and enable at bit 0
|
||||
};
|
||||
|
||||
static struct dram_base_mask_t get_dram_base_mask(u32 nodeid)
|
||||
{
|
||||
device_t dev;
|
||||
struct dram_base_mask_t d;
|
||||
#if defined(__PRE_RAM__)
|
||||
dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1);
|
||||
#else
|
||||
dev = __f1_dev[0];
|
||||
#endif // defined(__PRE_RAM__)
|
||||
|
||||
u32 temp;
|
||||
temp = pci_read_config32(dev, 0x44); //[39:24] at [31:16]
|
||||
d.mask = (temp & 0xffff0000); // mask out DramMask [26:24] too
|
||||
|
||||
temp = pci_read_config32(dev, 0x40); //[35:24] at [27:16]
|
||||
d.mask |= (temp & 1); // read enable bit
|
||||
|
||||
d.base = (temp & 0x0fff0000); // mask out DramBase [26:24) too
|
||||
|
||||
return d;
|
||||
}
|
||||
|
||||
#if CONFIG_EXT_CONF_SUPPORT
|
||||
static void set_addr_map_reg_4_6_in_one_node(u32 nodeid, u32 cfg_map_dest,
|
||||
u32 busn_min, u32 busn_max,
|
||||
u32 type)
|
||||
{
|
||||
device_t dev;
|
||||
u32 i;
|
||||
u32 tempreg;
|
||||
u32 index_min, index_max;
|
||||
u32 dest_min, dest_max;
|
||||
index_min = busn_min>>2; dest_min = busn_min - (index_min<<2);
|
||||
index_max = busn_max>>2; dest_max = busn_max - (index_max<<2);
|
||||
|
||||
// three case: index_min==index_max, index_min+1=index_max; index_min+1<index_max
|
||||
#if defined(__PRE_RAM__)
|
||||
dev = NODE_PCI(nodeid, 1);
|
||||
#else
|
||||
dev = __f1_dev[nodeid];
|
||||
#endif // defined(__PRE_RAM__)
|
||||
if(index_min== index_max) {
|
||||
pci_write_config32(dev, 0x110, index_min | (type<<28));
|
||||
tempreg = pci_read_config32(dev, 0x114);
|
||||
for(i=dest_min; i<=dest_max; i++) {
|
||||
tempreg &= ~(0xff<<(i*8));
|
||||
tempreg |= (cfg_map_dest<<(i*8));
|
||||
}
|
||||
pci_write_config32(dev, 0x110, index_min | (type<<28)); // do i need to write it again
|
||||
pci_write_config32(dev, 0x114, tempreg);
|
||||
} else if(index_min<index_max) {
|
||||
pci_write_config32(dev, 0x110, index_min | (type<<28));
|
||||
tempreg = pci_read_config32(dev, 0x114);
|
||||
for(i=dest_min; i<=3; i++) {
|
||||
tempreg &= ~(0xff<<(i*8));
|
||||
tempreg |= (cfg_map_dest<<(i*8));
|
||||
}
|
||||
pci_write_config32(dev, 0x110, index_min | (type<<28)); // do i need to write it again
|
||||
pci_write_config32(dev, 0x114, tempreg);
|
||||
|
||||
pci_write_config32(dev, 0x110, index_max | (type<<28));
|
||||
tempreg = pci_read_config32(dev, 0x114);
|
||||
for(i=0; i<=dest_max; i++) {
|
||||
tempreg &= ~(0xff<<(i*8));
|
||||
tempreg |= (cfg_map_dest<<(i*8));
|
||||
}
|
||||
pci_write_config32(dev, 0x110, index_max | (type<<28)); // do i need to write it again
|
||||
pci_write_config32(dev, 0x114, tempreg);
|
||||
if((index_max-index_min)>1) {
|
||||
tempreg = 0;
|
||||
for(i=0; i<=3; i++) {
|
||||
tempreg &= ~(0xff<<(i*8));
|
||||
tempreg |= (cfg_map_dest<<(i*8));
|
||||
}
|
||||
for(i=index_min+1; i<index_max;i++) {
|
||||
pci_write_config32(dev, 0x110, i | (type<<28));
|
||||
pci_write_config32(dev, 0x114, tempreg);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif // CONFIG_EXT_CONF_SUPPORT
|
||||
|
||||
#if defined(__PRE_RAM__)
|
||||
static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
|
||||
u32 io_min, u32 io_max, u32 nodes)
|
||||
{
|
||||
u32 i;
|
||||
u32 tempreg;
|
||||
device_t dev;
|
||||
|
||||
#if CONFIG_EXT_CONF_SUPPORT
|
||||
if(ht_c_index<4) {
|
||||
#endif
|
||||
/* io range allocation */
|
||||
tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit
|
||||
for(i=0; i<nodes; i++) {
|
||||
dev = NODE_PCI(i, 1);
|
||||
pci_write_config32(dev, 0xC4 + ht_c_index * 8, tempreg);
|
||||
}
|
||||
tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?
|
||||
for(i=0; i<nodes; i++){
|
||||
dev = NODE_PCI(i, 1);
|
||||
pci_write_config32(dev, 0xC0 + ht_c_index * 8, tempreg);
|
||||
}
|
||||
#if CONFIG_EXT_CONF_SUPPORT
|
||||
return;
|
||||
}
|
||||
|
||||
u32 cfg_map_dest;
|
||||
u32 j;
|
||||
|
||||
// if ht_c_index > 3, We should use extend space
|
||||
|
||||
if(io_min>io_max) return;
|
||||
|
||||
// for nodeid at first
|
||||
cfg_map_dest = (1<<7) | (1<<6) | (linkn<<0);
|
||||
|
||||
set_addr_map_reg_4_6_in_one_node(nodeid, cfg_map_dest, io_min, io_max, 4);
|
||||
|
||||
// all other nodes
|
||||
cfg_map_dest = (1<<7) | (0<<6) | (nodeid<<0);
|
||||
for(j = 0; j< nodes; j++) {
|
||||
if(j== nodeid) continue;
|
||||
set_addr_map_reg_4_6_in_one_node(j,cfg_map_dest, io_min, io_max, 4);
|
||||
}
|
||||
#endif // CONFIG_EXT_CONF_SUPPORT
|
||||
}
|
||||
|
||||
static void clear_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
|
||||
u32 io_min, u32 io_max, u32 nodes)
|
||||
{
|
||||
u32 i;
|
||||
device_t dev;
|
||||
#if CONFIG_EXT_CONF_SUPPORT
|
||||
if(ht_c_index<4) {
|
||||
#endif
|
||||
/* io range allocation */
|
||||
for(i=0; i<nodes; i++) {
|
||||
dev = NODE_PCI(i, 1);
|
||||
pci_write_config32(dev, 0xC4 + ht_c_index * 8, 0);
|
||||
pci_write_config32(dev, 0xC0 + ht_c_index * 8, 0);
|
||||
}
|
||||
#if CONFIG_EXT_CONF_SUPPORT
|
||||
return;
|
||||
}
|
||||
// : if hc_c_index > 3, We should use io_min, io_max to clear extend space
|
||||
u32 cfg_map_dest;
|
||||
u32 j;
|
||||
|
||||
// all nodes
|
||||
cfg_map_dest = 0;
|
||||
for(j = 0; j< nodes; j++) {
|
||||
set_addr_map_reg_4_6_in_one_node(j,cfg_map_dest, io_min, io_max, 4);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
#endif // defined(__PRE_RAM__)
|
||||
|
||||
#if !defined(__PRE_RAM__)
|
||||
static u32 get_io_addr_index(u32 nodeid, u32 linkn)
|
||||
{
|
||||
#if 0
|
||||
u32 index;
|
||||
|
||||
for(index=0; index<256; index++) {
|
||||
if((sysconf.conf_io_addrx[index+4] == 0)){
|
||||
sysconf.conf_io_addr[index+4] = (nodeid & 0x3f) ;
|
||||
sysconf.conf_io_addrx[index+4] = 1 | ((linkn & 0x7)<<4);
|
||||
return index;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
static u32 get_mmio_addr_index(u32 nodeid, u32 linkn)
|
||||
{
|
||||
#if 0
|
||||
u32 index;
|
||||
|
||||
for(index=0; index<64; index++) {
|
||||
if((sysconf.conf_mmio_addrx[index+8] == 0)){
|
||||
sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f) ;
|
||||
sysconf.conf_mmio_addrx[index+8] = 1 | ((linkn & 0x7)<<4);
|
||||
return index;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
|
||||
u32 io_min, u32 io_max)
|
||||
{
|
||||
|
||||
u32 tempreg;
|
||||
#if CONFIG_EXT_CONF_SUPPORT
|
||||
if(reg!=0x110) {
|
||||
#endif
|
||||
/* io range allocation */
|
||||
tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit
|
||||
pci_write_config32(__f1_dev[0], reg+4, tempreg);
|
||||
|
||||
tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?
|
||||
#if 0
|
||||
// FIXME: can we use VGA reg instead?
|
||||
if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
|
||||
printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link %s\n",
|
||||
__func__, dev_path(dev), link);
|
||||
tempreg |= PCI_IO_BASE_VGA_EN;
|
||||
}
|
||||
if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) {
|
||||
tempreg |= PCI_IO_BASE_NO_ISA;
|
||||
}
|
||||
#endif
|
||||
pci_write_config32(__f1_dev[0], reg, tempreg);
|
||||
#if CONFIG_EXT_CONF_SUPPORT
|
||||
return;
|
||||
}
|
||||
|
||||
u32 cfg_map_dest;
|
||||
u32 j;
|
||||
// if ht_c_index > 3, We should use extend space
|
||||
if(io_min>io_max) return;
|
||||
// for nodeid at first
|
||||
cfg_map_dest = (1<<7) | (1<<6) | (linkn<<0);
|
||||
|
||||
set_addr_map_reg_4_6_in_one_node(nodeid, cfg_map_dest, io_min, io_max, 4);
|
||||
#endif // CONFIG_EXT_CONF_SUPPORT
|
||||
}
|
||||
|
||||
static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes)
|
||||
{
|
||||
|
||||
u32 tempreg;
|
||||
#if CONFIG_EXT_CONF_SUPPORT
|
||||
if(reg!=0x110) {
|
||||
#endif
|
||||
/* io range allocation */
|
||||
tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit
|
||||
pci_write_config32(__f1_dev[0], reg+4, tempreg);
|
||||
tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00);
|
||||
pci_write_config32(__f1_dev[0], reg, tempreg);
|
||||
#if CONFIG_EXT_CONF_SUPPORT
|
||||
return;
|
||||
}
|
||||
|
||||
device_t dev;
|
||||
u32 j;
|
||||
// if ht_c_index > 3, We should use extend space
|
||||
// for nodeid at first
|
||||
u32 enable;
|
||||
|
||||
if(mmio_min>mmio_max) {
|
||||
return;
|
||||
}
|
||||
|
||||
enable = 1;
|
||||
|
||||
dev = __f1_dev[nodeid];
|
||||
tempreg = ((mmio_min>>3) & 0x1fffff00)| (1<<6) | (linkn<<0);
|
||||
pci_write_config32(dev, 0x110, index | (2<<28));
|
||||
pci_write_config32(dev, 0x114, tempreg);
|
||||
|
||||
tempreg = ((mmio_max>>3) & 0x1fffff00) | enable;
|
||||
pci_write_config32(dev, 0x110, index | (3<<28));
|
||||
pci_write_config32(dev, 0x114, tempreg);
|
||||
#endif // CONFIG_EXT_CONF_SUPPORT
|
||||
}
|
||||
|
||||
#endif // !defined(__PRE_RAM__)
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
/*
|
||||
*****************************************************************************
|
||||
*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
* ***************************************************************************
|
||||
*
|
||||
*/
|
||||
|
||||
#include <arch/io.h>
|
||||
#include <arch/romcc_io.h>
|
||||
#include <device/pci_def.h>
|
||||
|
||||
static void bootblock_northbridge_init(void) {
|
||||
}
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
struct northbridge_amd_agesa_family15tn_config
|
||||
{
|
||||
};
|
||||
|
||||
extern struct chip_operations northbridge_amd_agesa_family15tn_ops;
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,26 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef NORTHBRIDGE_AMD_AGESA_FAM15H_H
|
||||
#define NORTHBRIDGE_AMD_AGESA_FAM15H_H
|
||||
|
||||
static struct device_operations pci_domain_ops;
|
||||
static struct device_operations cpu_bus_ops;
|
||||
|
||||
#endif /* NORTHBRIDGE_AMD_AGESA_FAM15H_H */
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
config NORTHBRIDGE_AMD_AGESA_FAMILY15_TN_ROOT_COMPLEX
|
||||
bool
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
struct northbridge_amd_agesa_family15tn_root_complex_config
|
||||
{
|
||||
};
|
||||
|
||||
extern struct chip_operations northbridge_amd_agesa_family15tn_root_complex_ops;
|
||||
|
|
@ -115,6 +115,13 @@ void spi_write_enable(volatile u8 * spi_address)
|
|||
execute_command(spi_address);
|
||||
wait4command_complete(spi_address);
|
||||
}
|
||||
void spi_write_disable(volatile u8 * spi_address)
|
||||
{
|
||||
*spi_address = 0x04; /* Write Enable */
|
||||
*(spi_address + 1) = 0x0; /* RxByte=0, TxByte=0 */
|
||||
execute_command(spi_address);
|
||||
wait4command_complete(spi_address);
|
||||
}
|
||||
|
||||
void sector_erase_spi(volatile u8 * spi_address, u32 address)
|
||||
{
|
||||
|
|
|
|||
Loading…
Reference in New Issue