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rk3399: add definition for SP0 iomux 

This register is described in the TRM in section called
GRF_GPIO3D_IOMUX. Added definitions allow to configure the SPI0
interface.

BRANCH=none
BUG=chrome-os-partner:50645, chrome-os-partner:51537
TEST=with the rest of the patches applied it is possible to
     communicate over SPI0

Change-Id: Ieee3fcae6095020042b02673c7d863f398ed2eb4
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 8f155e3b47c9f44ad4e5a2513916572e7d5ec0ab
Original-Change-Id: Iea92971b0520dc4549cd0fd263dcb2098f80f6d6
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/349851
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://review.coreboot.org/15295
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Vadim Bendebury 2016-04-06 13:44:37 -07:00 committed by Martin Roth
parent 26588707c5
commit 2c109a74cb
1 changed files with 8 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
src/soc/rockchip/rk3399/include/soc/grf.h
View File

@ -128,7 +128,10 @@ struct rk3399_grf_regs {
u32 iomux_spi5; u32 iomux_spi5;
}; };
u32 gpio2d_iomux; u32 gpio2d_iomux;
u32 gpio3a_iomux; union {
u32 gpio3a_iomux;
u32 iomux_spi0;
};
u32 gpio3b_iomux; u32 gpio3b_iomux;
u32 gpio3c_iomux; u32 gpio3c_iomux;
union { union {
@ -341,11 +344,13 @@ static struct rk3399_pmusgrf_regs * const rk3399_pmusgrf = (void *)PMUSGRF_BASE;
#define IOMUX_UART2A RK_CLRSETBITS(3 << 2 | 3 << 0, 2 << 2 | 2 << 0) #define IOMUX_UART2A RK_CLRSETBITS(3 << 2 | 3 << 0, 2 << 2 | 2 << 0)
#define IOMUX_UART2B RK_CLRSETBITS(3 << 2 | 3 << 0, 2 << 2 | 2 << 0) #define IOMUX_UART2B RK_CLRSETBITS(3 << 2 | 3 << 0, 2 << 2 | 2 << 0)
#define IOMUX_UART2C RK_CLRSETBITS(3 << 8 | 3 << 6, 1 << 8 | 1 << 6) #define IOMUX_UART2C RK_CLRSETBITS(3 << 8 | 3 << 6, 1 << 8 | 1 << 6)
#define IOMUX_SPI2 RK_CLRSETBITS(0xff << 2, 1 << 8 | 1 << 6 |\ #define IOMUX_SPI0 RK_CLRSETBITS(0xff << 8, \
1 << 4 | 1 << 2) 2 << 14 | 2 << 12 | 2 << 10 | 2 << 8)
#define IOMUX_SPI1_RX RK_CLRSETBITS(3 << 14, 2 << 14) #define IOMUX_SPI1_RX RK_CLRSETBITS(3 << 14, 2 << 14)
#define IOMUX_SPI1_CSCLKTX RK_CLRSETBITS(0x3f << 0, 2 << 4 |\ #define IOMUX_SPI1_CSCLKTX RK_CLRSETBITS(0x3f << 0, 2 << 4 |\
2 << 2 | 2 << 0) 2 << 2 | 2 << 0)
#define IOMUX_SPI2 RK_CLRSETBITS(0xff << 2, 1 << 8 | 1 << 6 |\
1 << 4 | 1 << 2)
#define IOMUX_SPI5 RK_CLRSETBITS(0xff << 8, \ #define IOMUX_SPI5 RK_CLRSETBITS(0xff << 8, \
2 << 14 | 2 << 12 | 2 << 10 | 2 << 8) 2 << 14 | 2 << 12 | 2 << 10 | 2 << 8)
#define IOMUX_SDMMC RK_CLRSETBITS(0xfff, 1 << 10 | 1 << 8 | 1 << 6 |\ #define IOMUX_SDMMC RK_CLRSETBITS(0xfff, 1 << 10 | 1 << 8 | 1 << 6 |\