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SMM on AMD K8 Part 2/2 

Signed-off-by: Rudolf Marek <r.marek@assembler.cz> 
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6202 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Rudolf Marek 2010-12-18 23:30:59 +00:00 committed by Stefan Reinauer
parent cadc545838
commit 2c3662710a
2 changed files with 19 additions and 33 deletions
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48
src/cpu/amd/smm/smm_init.c
View File

@ -57,13 +57,13 @@ void smm_init(void)
smm_handler_copied = 1; smm_handler_copied = 1;
/* MTRR changes don't like an enabled cache */
disable_cache();
/* Back up MSRs for later restore */ /* Back up MSRs for later restore */
syscfg_orig = rdmsr(SYSCFG_MSR); syscfg_orig = rdmsr(SYSCFG_MSR);
mtrr_aseg_orig = rdmsr(MTRRfix16K_A0000_MSR); mtrr_aseg_orig = rdmsr(MTRRfix16K_A0000_MSR);
/* MTRR changes don't like an enabled cache */
disable_cache();
msr = syscfg_orig; msr = syscfg_orig;
/* Allow changes to MTRR extended attributes */ /* Allow changes to MTRR extended attributes */
msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
@ -78,60 +78,46 @@ void smm_init(void)
msr.lo = 0x18181818; msr.lo = 0x18181818;
msr.hi = 0x18181818; msr.hi = 0x18181818;
wrmsr(MTRRfix16K_A0000_MSR, msr); wrmsr(MTRRfix16K_A0000_MSR, msr);
enable_cache();
/* disable the extended features */ /* enable the extended features */
msr = syscfg_orig; msr = syscfg_orig;
msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
msr.lo |= SYSCFG_MSR_MtrrFixDramEn; msr.lo |= SYSCFG_MSR_MtrrFixDramEn;
wrmsr(SYSCFG_MSR, msr); wrmsr(SYSCFG_MSR, msr);
/* enable the SMM memory window */ enable_cache();
// TODO does "Enable ASEG SMRAM Range" have to happen on
// every CPU core?
msr = rdmsr(SMM_MASK_MSR);
msr.lo |= (1 << 0); // Enable ASEG SMRAM Range
msr.lo &= ~(1 << 2); // Open ASEG SMRAM Range
wrmsr(SMM_MASK_MSR, msr);
/* copy the real SMM handler */ /* copy the real SMM handler */
memcpy((void *)SMM_BASE, &_binary_smm_start, (size_t)&_binary_smm_size); memcpy((void *)SMM_BASE, &_binary_smm_start, (size_t)&_binary_smm_size);
wbinvd(); wbinvd();
msr = rdmsr(SMM_MASK_MSR);
msr.lo |= ~(1 << 2); // Close ASEG SMRAM Range
wrmsr(SMM_MASK_MSR, msr);
/* Change SYSCFG so we can restore the MTRR */
msr = syscfg_orig;
msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn;
wrmsr(SYSCFG_MSR, msr);
/* Restore MTRR */ /* Restore MTRR */
disable_cache(); disable_cache();
wrmsr(MTRRfix16K_A0000_MSR, mtrr_aseg_orig);
/* Restore SYSCFG */ /* Restore SYSCFG */
wrmsr(SYSCFG_MSR, syscfg_orig); wrmsr(SYSCFG_MSR, syscfg_orig);
wrmsr(MTRRfix16K_A0000_MSR, mtrr_aseg_orig);
enable_cache(); enable_cache();
} }
/* But set SMM base address on all CPUs/cores */ /* But set SMM base address on all CPUs/cores */
msr = rdmsr(SMM_BASE_MSR); msr = rdmsr(SMM_BASE_MSR);
msr.lo = SMM_BASE - (lapicid() * 0x400); msr.lo = SMM_BASE - (lapicid() * 0x400);
wrmsr(SMM_BASE_MSR, msr); wrmsr(SMM_BASE_MSR, msr);
}
void smm_lock(void) /* enable the SMM memory window */
{ msr = rdmsr(SMM_MASK_MSR);
// TODO I think this should be running on each CPU msr.lo |= (1 << 0); // Enable ASEG SMRAM Range
msr_t msr; wrmsr(SMM_MASK_MSR, msr);
printk(BIOS_DEBUG, "Locking SMM.\n");
/* Set SMMLOCK to avoid exploits messing with SMM */ /* Set SMMLOCK to avoid exploits messing with SMM */
msr = rdmsr(HWCR_MSR); msr = rdmsr(HWCR_MSR);
msr.lo |= (1 << 0); msr.lo |= (1 << 0);
wrmsr(HWCR_MSR, msr); wrmsr(HWCR_MSR, msr);
} }
void smm_lock(void)
{
/* We lock SMM per CPU core */
}

4
src/southbridge/via/vt8237r/smihandler.c
View File

@ -208,9 +208,9 @@ smi_handler_t southbridge_smi[32] = {
NULL, // [1] NULL, // [1]
NULL, // [2] NULL, // [2]
NULL, // [3] NULL, // [3]
southbridge_smi_cmd, // [4] NULL, // [4]
NULL, // [5] NULL, // [5]
NULL, // [6] southbridge_smi_cmd, // [6]
NULL, // [7] NULL, // [7]
NULL, // [8] NULL, // [8]
NULL, // [9] NULL, // [9]