soc/intel/common/block/gpio: Allow GPI to be dual-routed

This change adds new macros to GPIO common library helpers to allow
a GPI pad to be dual routed using PAD_CFG_GPI_DUAL_ROUTE. It also adds
a helper macro to configure a pad for IRQ and wake.

Above macros are guarded using a newly added Kconfig option
SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT that is selected only
by SoCs that have been validated to allow dual route of
GPIs. Currently, this config is selected only for APL/GLK/SKL/KBL that
have been validated to work with dual-routing of GPIs for IRQ and
wake.

BUG=b:117553222

Change-Id: Iaa623d2d78a50f1504e3abe9a47a5a663693aead
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/29188
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/apollolake/Kconfig

@@ -75,6 +75,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_BLOCK_DSP
 	select SOC_INTEL_COMMON_BLOCK_FAST_SPI
 	select SOC_INTEL_COMMON_BLOCK_GPIO
+	select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
 	select SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES
 	select SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG
 	select SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY

src/soc/intel/common/block/gpio/Kconfig

@@ -42,3 +42,10 @@ config SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES
 	depends on SOC_INTEL_COMMON_BLOCK_GPIO
 	bool
 	default n
+
+# Indicate if SoC supports dual-routing of GPIOs (to different paths like SCI,
+# NMI, SMI, IOAPIC). This is required to support IRQ and wake on the same pad.
+config SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
+	depends on SOC_INTEL_COMMON_BLOCK_GPIO
+	bool
+	default n

src/soc/intel/common/block/include/intelblocks/gpio_defs.h

@@ -130,6 +130,14 @@
 				PAD_CFG0_TRIG_##trig | \
 				PAD_CFG0_RX_POL_##inv)
 
+#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT)
+#define PAD_IRQ_CFG_DUAL_ROUTE(route1, route2, trig, inv)  \
+				(PAD_CFG0_ROUTE_##route1 | \
+				PAD_CFG0_ROUTE_##route2 | \
+				PAD_CFG0_TRIG_##trig | \
+				PAD_CFG0_RX_POL_##inv)
+#endif /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT */
+
 #define _PAD_CFG_STRUCT(__pad, __config0, __config1)	\
 	{					\
 		.pad = __pad,			\
@@ -334,4 +342,16 @@
 		PAD_IRQ_CFG(NMI, trig, inv), PAD_PULL(pull) | \
 		PAD_IOSSTATE(TxDRxE))
 
+#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT)
+#define PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, route1, route2) \
+	_PAD_CFG_STRUCT(pad,						\
+		PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
+		PAD_IRQ_CFG_DUAL_ROUTE(route1, route2,  trig, inv), \
+		PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE))
+
+#define PAD_CFG_GPI_IRQ_WAKE(pad, pull, rst, trig, inv)	\
+	PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, IOAPIC, SCI)
+
+#endif /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT */
+
 #endif /* _SOC_BLOCK_GPIO_DEFS_H_ */

src/soc/intel/skylake/Kconfig

@@ -57,6 +57,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
 	select SOC_INTEL_COMMON_BLOCK_CPU
 	select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
+	select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
 	select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS
 	select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL
 	select SOC_INTEL_COMMON_BLOCK_GSPI