intel/nehalem post-car: Use postcar_frame for MTRR setup

Adapt implementation from skylake to prepare for removal of HIGH_MEMORY_SAVE
and moving on to RELOCATABLE_RAMSTAGE. With the change, CBMEM and SMM regions
are set to WRBACK with MTRRs and romstage ram stack is moved to CBMEM.

Change-Id: I84f6fa6f37a7348b2d4ad9f08a18bebe4b1e34e2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

src/cpu/intel/model_2065x/cache_as_ram.inc

@@ -170,8 +170,8 @@ before_romstage:
 	/* Call romstage.c main function. */
 	call	romstage_main
 	/* Save return value from romstage_main. It contains the stack to use
-	 * after cache-as-ram is torn down.
-	 */
+	 * after cache-as-ram is torn down. It also contains the information
+	 * for setting up MTRRs. */
 	movl	%eax, %esp
 
 	post_code(0x30)
@@ -220,31 +220,48 @@ before_romstage:
 
 	post_code(0x38)
 
-	/* Enable Write Back and Speculative Reads for the first MB
-	 * and ramstage.
-	 */
+	/* Clear all of the variable MTRRs. */
+	popl	%ebx
 	movl	$MTRR_PHYS_BASE(0), %ecx
-	movl	$(0x00000000 | MTRR_TYPE_WRBACK), %eax
-	xorl	%edx, %edx
-	wrmsr
-	movl	$MTRR_PHYS_MASK(0), %ecx
-	movl	$(~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax
-	movl	$CPU_PHYSMASK_HI, %edx	// 36bit address space
-	wrmsr
+	clr	%eax
+	clr	%edx
 
-#if CACHE_ROM_SIZE
-	/* Enable Caching and speculative Reads for the
-	 * complete ROM now that we actually have RAM.
-	 */
-	movl	$MTRR_PHYS_BASE(1), %ecx
-	movl	$(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax
-	xorl	%edx, %edx
+1:
+	testl	%ebx, %ebx
+	jz	1f
+	wrmsr			/* Write MTRR base. */
+	inc	%ecx
+	wrmsr			/* Write MTRR mask. */
+	inc	%ecx
+	dec	%ebx
+	jmp	1b
+
+1:
+	/* Get number of MTRRs. */
+	popl	%ebx
+	movl	$MTRR_PHYS_BASE(0), %ecx
+2:
+	testl	%ebx, %ebx
+	jz	2f
+
+	/* Low 32 bits of MTRR base. */
+	popl	%eax
+	/* Upper 32 bits of MTRR base. */
+	popl	%edx
+	/* Write MTRR base. */
 	wrmsr
-	movl	$MTRR_PHYS_MASK(1), %ecx
-	movl	$(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
-	movl	$CPU_PHYSMASK_HI, %edx
+	inc	%ecx
+	/* Low 32 bits of MTRR mask. */
+	popl	%eax
+	/* Upper 32 bits of MTRR mask. */
+	popl	%edx
+	/* Write MTRR mask. */
 	wrmsr
-#endif
+	inc	%ecx
+
+	dec	%ebx
+	jmp	2b
+2:
 
 	post_code(0x39)
 

src/mainboard/lenovo/x201/romstage.c

@@ -279,12 +279,9 @@ void mainboard_romstage_entry(unsigned long bist)
 		outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
 	}
 
-
 	romstage_handoff_init(s3resume);
 
-	if (s3resume)
-		acpi_prepare_for_resume();
-	else
+	if (!s3resume)
 		quick_ram_check();
 
 #if IS_ENABLED(CONFIG_LPC_TPM)

src/mainboard/packardbell/ms2290/romstage.c

@@ -269,11 +269,8 @@ void mainboard_romstage_entry(unsigned long bist)
 		outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
 	}
 
-
 	romstage_handoff_init(s3resume);
 
-	if (s3resume)
-		acpi_prepare_for_resume();
-	else
+	if (!s3resume)
 		quick_ram_check();
 }

src/northbridge/intel/nehalem/Kconfig

@@ -20,8 +20,8 @@ config NORTHBRIDGE_INTEL_NEHALEM
 	select INTEL_EDID
 	select TSC_MONOTONIC_TIMER
 	select INTEL_GMA_ACPI
+	select RELOCATABLE_RAMSTAGE
 	select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE
-	select ACPI_HUGE_LOWMEM_BACKUP
 	select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
 	select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
 

src/northbridge/intel/nehalem/ram_calc.c

@@ -1,6 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
+ * Copyright (C) 2012 ChromeOS Authors
  * Copyright (C) 2013 Vladimir Serbinenko.
  *
  * This program is free software; you can redistribute it and/or modify
@@ -15,9 +16,13 @@
 
 #define __SIMPLE_DEVICE__
 
+#include <arch/cpu.h>
 #include <arch/io.h>
 #include <cbmem.h>
+#include <console/console.h>
 #include <cpu/intel/romstage.h>
+#include <cpu/x86/mtrr.h>
+#include <program_loading.h>
 #include "nehalem.h"
 
 static uintptr_t smm_region_start(void)
@@ -32,7 +37,35 @@ void *cbmem_top(void)
 	return (void *) smm_region_start();
 }
 
+#define ROMSTAGE_RAM_STACK_SIZE 0x5000
+
+/* setup_stack_and_mtrrs() determines the stack to use after
+ * cache-as-ram is torn down as well as the MTRR settings to use. */
 void *setup_stack_and_mtrrs(void)
 {
-	return (void*)CONFIG_RAMTOP;
+	struct postcar_frame pcf;
+	uintptr_t top_of_ram;
+
+	if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE))
+		die("Unable to initialize postcar frame.\n");
+
+	/* Cache the ROM as WP just below 4GiB. */
+	postcar_frame_add_mtrr(&pcf, -CACHE_ROM_SIZE, CACHE_ROM_SIZE,
+		MTRR_TYPE_WRPROT);
+
+	/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
+	postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
+
+	/* Cache at least 8 MiB below the top of ram, and at most 8 MiB
+	 * above top of the ram. This satisfies MTRR alignment requirement
+	 * with different TSEG size configurations.
+	 */
+	top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB);
+	postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK);
+	postcar_frame_add_mtrr(&pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK);
+
+	/* Save the number of MTRRs to setup. Return the stack location
+	 * pointing to the number of MTRRs.
+	 */
+	return postcar_commit_mtrrs(&pcf);
 }