util/spd_tools: Add LP5 support for ADL
Add LP5 support to spd_tools. Currently, only Intel Alder Lake (ADL) is supported. The SPDs are generated based on a combination of: - The LPDDR5 spec JESD209-5B. - The SPD spec SPD4.1.2.M-2 (the LPDDR3/4 spec is used since JEDEC has not released an SPD spec for LPDDR5). - Intel recommendations in advisory #616599. BUG=b:201234943, b:198704251 TEST=Generate the SPD and manifests for a test part, and check that the SPD matches Intel's expectation. More details in CB:58680. Change-Id: Ic1e68d44f7c0ad64aa9904b7e1297d24bd5db56e Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This commit is contained in:
Reka Norman
Patrick Georgi
parent
e5be13e46b
commit
2c439adb51
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@ -8,6 +8,9 @@ The memory technologies currently supported are:
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* LPDDR4x - based on the JESD209-4C spec and Intel recommendations
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(docs #616599, #610202, #634730).
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* DDR4 - based on the JESD79-4C and Jedec 4.1.2.L-5 R29 v103 specs.
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* LPDDR5 - based on the LPDDR5 spec JESD209-5B, the SPD spec SPD4.1.2.M-2 (the
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LPDDR3/4 spec is used since JEDEC has not released an SPD spec for LPDDR5),
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and Intel recommendations in advisory #616599.
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There are two tools provided to assist with generating SPDs and Makefiles to
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integrate into the coreboot build. These tools can also be used to allocate DRAM
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@ -292,6 +295,100 @@ string like "9 10 11 12 14".
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}
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```
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### LP5 attributes
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#### Mandatory
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* `densityPerDieGb`: Density per die in Gb. Valid values: `4, 6, 8, 12, 16,
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24, 32` Gb per die.
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* `diesPerPackage`: Number of physical dies in each SDRAM package. Valid
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values: `2, 4, 8` dies per package.
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* `bitWidthPerChannel`: Width of each physical channel. Valid values: `8, 16`
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bits.
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* `ranksPerChannel`: Number of ranks per physical channel. Valid values: `1,
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2`. If the channels across multiple dies share the same DQ/DQS pins but use
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a separate CS, then ranks is 2 else it is 1.
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* `speedMbps`: Maximum data rate supported by the part in Mbps. Valid values:
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`5500, 6400` Mbps.
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#### Optional
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* `trfcabNs`: Minimum Refresh Recovery Delay Time (tRFCab) for all banks in
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nanoseconds. As per JESD209-5B, this is dependent on the density per die.
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Default values used:
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* 4 Gb : 180 ns
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* 6 Gb : 210 ns
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* 8 Gb : 210 ns
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* 12 Gb: 280 ns
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* 16 Gb: 280 ns
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* 24 Gb: 380 ns
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* 32 Gb: 380 ns
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* `trfcpbNs`: Minimum Refresh Recovery Delay Time (tRFCpb) per bank in
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nanoseconds. As per JESD209-5B, this is dependent on the density per die.
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Default values used:
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* 4 Gb : 90 ns
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* 6 Gb : 120 ns
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* 8 Gb : 120 ns
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* 12 Gb: 140 ns
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* 16 Gb: 140 ns
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* 24 Gb: 190 ns
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* 32 Gb: 190 ns
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* `trpabMinNs`: Minimum Row Precharge Delay Time (tRPab) for all banks in
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nanoseconds. As per JESD209-5B, this is max(21ns, 2nCK), which defaults to
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`21 ns`.
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* `trppbMinNs`: Minimum Row Precharge Delay Time (tRPpb) per bank in
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nanoseconds. As per JESD209-5B, this is max(18ns, 2nCK) which defaults to
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`18 ns`.
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* `tckMinPs`: SDRAM minimum cycle time (tCKmin) value in picoseconds. LPDDR5
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has two clocks: the command/addrees clock (CK) and the data clock (WCK).
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They are related by the WCK:CK ratio, which can be either 4:1 or 2:1. For
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LPDDR5, tCKmin is the CK period, which can be calculated from the
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`speedMbps` attribute and the WCK:CK ratio as follows: `tCKmin = 1 /
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(speedMbps / 2 / WCK:CK)`. The default values used are for a 4:1 WCK:CK
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ratio:
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* 6400 Mbps: 1250 ps
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* 5500 Mbps: 1455 ps
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* `taaMinPs`: Minimum CAS Latency Time(tAAmin) in picoseconds. This value
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defaults to nck * tCKmin, where nck is maximum CAS latency, and is
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determined from the `speedMbps` attribute as per JESD209-5B:
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* 6400 Mbps: 17
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* 5500 Mbps: 15
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* `trcdMinNs`: Minimum RAS# to CAS# Delay Time (tRCDmin) in nanoseconds. As
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per JESD209-5B, this is max(18ns, 2nCK) which defaults to `18 ns`.
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#### Example `memory_parts.json`
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```
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{
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"parts": [
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{
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"name": "MT62F1G32D4DR-031 WT:B",
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"attribs": {
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"densityPerDieGb": 8,
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"diesPerPackage": 4,
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"bitWidthPerChannel": 16,
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"ranksPerChannel": 2,
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"speedMbps": 6400
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}
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},
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]
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}
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```
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### Output
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The `spd_gen` tool generates the directory structure shown below. The inputs to
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@ -45,6 +45,7 @@ var supportedPlatforms = [...]string{
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var supportedMemTechs = [...]string{
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"lp4x",
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"ddr4",
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"lp5",
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}
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func usage() {
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@ -0,0 +1,617 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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package main
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import (
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"encoding/json"
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"fmt"
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)
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/* ------------------------------------------------------------------------------------------ */
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/* LP5-defined types */
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/* ------------------------------------------------------------------------------------------ */
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type lp5 struct {
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}
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type LP5MemAttributes struct {
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/* Primary attributes - must be provided by JSON file for each part */
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DensityPerDieGb int
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DiesPerPackage int
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BitWidthPerChannel int
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RanksPerChannel int
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SpeedMbps int
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/*
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* All the following parameters are optional and required only if the part requires
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* special parameters as per the datasheet.
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*/
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/* Timing parameters */
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TRFCABNs int
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TRFCPBNs int
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TRPABMinNs int
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TRPPBMinNs int
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TCKMinPs int
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TAAMinPs int
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TRCDMinNs int
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}
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type LP5DensityParams struct {
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DensityEncoding byte
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RowAddressBitsx8Channel int
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RowAddressBitsx16Channel int
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TRFCABNs int
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TRFCPBNs int
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}
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type LP5SpeedParams struct {
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TCKMinPs int
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MaxCASLatency int
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}
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type LP5SPDAttribFunc func(*LP5MemAttributes) byte
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type LP5SPDAttribTableEntry struct {
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constVal byte
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getVal LP5SPDAttribFunc
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}
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/* ------------------------------------------------------------------------------------------ */
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/* Constants */
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/* ------------------------------------------------------------------------------------------ */
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const (
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/* SPD Byte Index */
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LP5SPDIndexSize = 0
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LP5SPDIndexRevision = 1
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LP5SPDIndexMemoryType = 2
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LP5SPDIndexModuleType = 3
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LP5SPDIndexDensityBanks = 4
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LP5SPDIndexAddressing = 5
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LP5SPDIndexPackageType = 6
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LP5SPDIndexOptionalFeatures = 7
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LP5SPDIndexModuleOrganization = 12
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LP5SPDIndexBusWidth = 13
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LP5SPDIndexTimebases = 17
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LP5SPDIndexTCKMin = 18
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LP5SPDIndexTAAMin = 24
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LP5SPDIndexTRCDMin = 26
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LP5SPDIndexTRPABMin = 27
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LP5SPDIndexTRPPBMin = 28
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LP5SPDIndexTRFCABMinLSB = 29
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LP5SPDIndexTRFCABMinMSB = 30
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LP5SPDIndexTRFCPBMinLSB = 31
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LP5SPDIndexTRFCPBMinMSB = 32
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LP5SPDIndexTRPPBMinFineOffset = 120
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LP5SPDIndexTRPABMinFineOffset = 121
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LP5SPDIndexTRCDMinFineOffset = 122
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LP5SPDIndexTAAMinFineOffset = 123
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LP5SPDIndexTCKMinFineOffset = 125
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LP5SPDIndexManufacturerPartNumberStartByte = 329
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LP5SPDIndexManufacturerPartNumberEndByte = 348
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/* SPD Byte Value */
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/*
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* From JEDEC spec:
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* 6:4 (Bytes total) = 2 (512 bytes)
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* 3:0 (Bytes used) = 3 (384 bytes)
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* Set to 0x23 for LPDDR5.
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*/
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LP5SPDValueSize = 0x23
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/*
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* Revision 1.0.
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*/
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LP5SPDValueRevision = 0x10
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/*
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* As per advisory #616599, ADL MRC expects LPDDR5 memory type = 0x13.
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*/
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LP5SPDValueMemoryType = 0x13
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/*
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* From JEDEC spec:
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* 7:7 (Hybrid) = 0 (Not hybrid)
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* 6:4 (Hybrid media) = 000 (Not hybrid)
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* 3:0 (Base Module Type) = 1110 (Non-DIMM solution)
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*
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* This is dependent on hardware design. LPDDR5 only has memory down solution.
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* Hence this is not hybrid non-DIMM solution.
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* Set to 0x0E.
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*/
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LP5SPDValueModuleType = 0x0e
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/*
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* From JEDEC spec:
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* 5:4 (Maximum Activate Window) = 00 (8192 * tREFI)
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* 3:0 (Maximum Activate Count) = 1000 (Unlimited MAC)
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* Set to 0x08.
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*/
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LP5SPDValueOptionalFeatures = 0x08
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/*
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* For ADL (as per advisory #616599):
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* 7:5 (Number of system channels) = 000 (1 channel always)
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* 4:3 (Bus width extension) = 00 (no ECC)
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* 2:0 (Bus width) = 001 (x16 always)
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* Set to 0x01.
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*/
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LP5SPDValueBusWidth = 0x01
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/*
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* From JEDEC spec:
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* 3:2 (MTB) = 00 (0.125ns)
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* 1:0 (FTB) = 00 (1ps)
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* Set to 0x00.
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*/
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LP5SPDValueTimebases = 0x00
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/* As per JEDEC spec, unused digits of manufacturer part number are left as blank. */
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LP5SPDValueManufacturerPartNumberBlank = 0x20
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)
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const (
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/*
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* LPDDR5 has a flexible bank architecture with three programmable bank modes: BG, 8B, 16B.
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* ADL will use 8B mode for all parts.
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*
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* From JEDEC spec:
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* 7:6 (Bank Group Bits) = 00 (no bank groups)
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* 5:4 (Bank Address Bits) = 01 (8 banks)
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* Set bits 7:4 to 0b0001.
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*/
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LP5BankGroupsBanks = 0x1
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/*
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* Tables 8 and 9 from JESD209-5B.
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* ADL uses 8B mode for all parts. The column addresses are the same for x8 and x16.
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* Effective column address bits = column address bits + burst address bits = 6 + 5 = 11.
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* As per JESD 21-C, this is encoded as 0b010.
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*/
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LP5ColumnAddressBits = 0x2
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)
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/* ------------------------------------------------------------------------------------------ */
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/* Global variables */
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/* ------------------------------------------------------------------------------------------ */
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var LP5PlatformSetMap = map[int][]int{
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0: {PlatformADL},
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}
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var LP5PartAttributeMap = map[string]LP5MemAttributes{}
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var LP5CurrSet int
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/*
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* DensityEncoding: Maps the die density in Gb to the SPD encoding of the die density
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* as per JESD 21-C.
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*
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* RowAddressBits: Maps the die density to the number of row address bits.
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* Tables 6-11 in JESD209-5B (same for all three bank modes).
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*
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* TRFCABNs/TRFCPBNs: Maps the die density to the refresh timings.
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* Tables 235 and 236 in JESD209-5B (same for all three bank modes).
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*/
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var LP5DensityGbToSPDEncoding = map[int]LP5DensityParams{
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4: {
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DensityEncoding: 0x4,
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RowAddressBitsx8Channel: 15,
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RowAddressBitsx16Channel: 14,
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TRFCABNs: 180,
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TRFCPBNs: 90,
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},
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6: {
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DensityEncoding: 0xb,
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RowAddressBitsx8Channel: 16,
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RowAddressBitsx16Channel: 15,
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TRFCABNs: 210,
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TRFCPBNs: 120,
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},
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8: {
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DensityEncoding: 0x5,
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RowAddressBitsx8Channel: 16,
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RowAddressBitsx16Channel: 15,
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TRFCABNs: 210,
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TRFCPBNs: 120,
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},
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12: {
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DensityEncoding: 0x8,
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RowAddressBitsx8Channel: 17,
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RowAddressBitsx16Channel: 16,
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TRFCABNs: 280,
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TRFCPBNs: 140,
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},
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16: {
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DensityEncoding: 0x6,
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RowAddressBitsx8Channel: 17,
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RowAddressBitsx16Channel: 16,
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TRFCABNs: 280,
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TRFCPBNs: 140,
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},
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24: {
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DensityEncoding: 0x9,
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RowAddressBitsx8Channel: 18,
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RowAddressBitsx16Channel: 17,
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TRFCABNs: 380,
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TRFCPBNs: 190,
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},
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32: {
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DensityEncoding: 0x7,
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RowAddressBitsx8Channel: 18,
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RowAddressBitsx16Channel: 17,
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TRFCABNs: 380,
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TRFCPBNs: 190,
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},
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}
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/*
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* Maps the number of row address bits to the SPD encoding as per JESD 21-C.
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*/
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var LP5RowAddressBitsEncoding = map[int]byte{
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14: 0x2,
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15: 0x3,
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16: 0x4,
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17: 0x5,
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18: 0x6,
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}
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/*
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* TCKMinPs:
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* LPDDR5 has two clocks: the command/address clock (CK) and the data clock (WCK). They are
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* related by the WCK:CK ratio, which can be either 4:1 or 2:1. On ADL, 4:1 is used.
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* For ADL, the MRC expects the tCKmin to encode the CK period. This is calculated as:
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* tCKmin = 1 / CK rate
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* = 1 / (WCK rate / WCK:CK)
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* = 1 / (speed grade / 2 / WCK:CK) // "double data rate"
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*
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* MaxCASLatency:
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* From Table 220 of JESD209-5B, using a 4:1 WCK:CK ratio and Set 0.
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*/
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var LP5SpeedMbpsToSPDEncoding = map[int]LP5SpeedParams{
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6400: {
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TCKMinPs: 1250, /* 1 / (6400 / 2 / 4) */
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MaxCASLatency: 17,
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},
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5500: {
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TCKMinPs: 1455, /* 1 / (5500 / 2 / 4) */
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MaxCASLatency: 15,
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},
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}
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var LP5SPDAttribTable = map[int]LP5SPDAttribTableEntry{
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LP5SPDIndexSize: {constVal: LP5SPDValueSize},
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LP5SPDIndexRevision: {constVal: LP5SPDValueRevision},
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LP5SPDIndexMemoryType: {constVal: LP5SPDValueMemoryType},
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LP5SPDIndexModuleType: {constVal: LP5SPDValueModuleType},
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LP5SPDIndexDensityBanks: {getVal: LP5EncodeDensityBanks},
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LP5SPDIndexAddressing: {getVal: LP5EncodeSdramAddressing},
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LP5SPDIndexPackageType: {getVal: LP5EncodePackageType},
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LP5SPDIndexOptionalFeatures: {constVal: LP5SPDValueOptionalFeatures},
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LP5SPDIndexModuleOrganization: {getVal: LP5EncodeModuleOrganization},
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LP5SPDIndexBusWidth: {constVal: LP5SPDValueBusWidth},
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LP5SPDIndexTimebases: {constVal: LP5SPDValueTimebases},
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LP5SPDIndexTCKMin: {getVal: LP5EncodeTCKMin},
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LP5SPDIndexTCKMinFineOffset: {getVal: LP5EncodeTCKMinFineOffset},
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LP5SPDIndexTAAMin: {getVal: LP5EncodeTAAMin},
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LP5SPDIndexTAAMinFineOffset: {getVal: LP5EncodeTAAMinFineOffset},
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LP5SPDIndexTRCDMin: {getVal: LP5EncodeTRCDMin},
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LP5SPDIndexTRCDMinFineOffset: {getVal: LP5EncodeTRCDMinFineOffset},
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LP5SPDIndexTRPABMin: {getVal: LP5EncodeTRPABMin},
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LP5SPDIndexTRPABMinFineOffset: {getVal: LP5EncodeTRPABMinFineOffset},
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LP5SPDIndexTRPPBMin: {getVal: LP5EncodeTRPPBMin},
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LP5SPDIndexTRPPBMinFineOffset: {getVal: LP5EncodeTRPPBMinFineOffset},
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LP5SPDIndexTRFCABMinLSB: {getVal: LP5EncodeTRFCABMinLsb},
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LP5SPDIndexTRFCABMinMSB: {getVal: LP5EncodeTRFCABMinMsb},
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LP5SPDIndexTRFCPBMinLSB: {getVal: LP5EncodeTRFCPBMinLsb},
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LP5SPDIndexTRFCPBMinMSB: {getVal: LP5EncodeTRFCPBMinMsb},
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}
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/* ------------------------------------------------------------------------------------------ */
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/* Functions */
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/* ------------------------------------------------------------------------------------------ */
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func LP5EncodeDensityBanks(memAttribs *LP5MemAttributes) byte {
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var b byte
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// 3:0 Density per die.
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b = LP5DensityGbToSPDEncoding[memAttribs.DensityPerDieGb].DensityEncoding
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// 5:4 Bank address bits.
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// 7:6 Bank group bits.
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b |= LP5BankGroupsBanks << 4
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return b
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}
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|
||||
func LP5EncodeSdramAddressing(memAttribs *LP5MemAttributes) byte {
|
||||
var b byte
|
||||
|
||||
// 2:0 Column address bits.
|
||||
b = LP5ColumnAddressBits
|
||||
|
||||
// 5:3 Row address bits.
|
||||
density := memAttribs.DensityPerDieGb
|
||||
var rowAddressBits int
|
||||
if memAttribs.BitWidthPerChannel == 8 {
|
||||
rowAddressBits = LP5DensityGbToSPDEncoding[density].RowAddressBitsx8Channel
|
||||
} else {
|
||||
rowAddressBits = LP5DensityGbToSPDEncoding[density].RowAddressBitsx16Channel
|
||||
}
|
||||
b |= LP5RowAddressBitsEncoding[rowAddressBits] << 3
|
||||
|
||||
return b
|
||||
}
|
||||
|
||||
func LP5EncodePackageType(memAttribs *LP5MemAttributes) byte {
|
||||
var b byte
|
||||
|
||||
// 1:0 Signal loading index.
|
||||
b = 1
|
||||
|
||||
// 3:2 Channels per package.
|
||||
// Channels per package = package width (e.g. x32) / bitWidthPerChannel (x8 or x16).
|
||||
// This can equivalently be calculated as diesPerPackage / ranksPerChannel.
|
||||
// This calculation is used to avoid adding a redundant attribute for package width.
|
||||
channels := memAttribs.DiesPerPackage / memAttribs.RanksPerChannel
|
||||
b |= byte(channels>>1) << 2
|
||||
|
||||
// 6:4 Dies per package.
|
||||
b |= (byte(memAttribs.DiesPerPackage) - 1) << 4
|
||||
|
||||
// 7:7 Package type.
|
||||
var packageType byte
|
||||
if memAttribs.DiesPerPackage > 1 {
|
||||
packageType = 1 // Non-Monolithic
|
||||
} else {
|
||||
packageType = 0 // Monolithic
|
||||
}
|
||||
b |= packageType << 7
|
||||
|
||||
return b
|
||||
}
|
||||
|
||||
func LP5EncodeModuleOrganization(memAttribs *LP5MemAttributes) byte {
|
||||
var b byte
|
||||
|
||||
// 2:0 Device data width per channel
|
||||
b = byte(memAttribs.BitWidthPerChannel / 8)
|
||||
|
||||
// 5:3 Package ranks per channel
|
||||
b |= byte(memAttribs.RanksPerChannel-1) << 3
|
||||
|
||||
return b
|
||||
}
|
||||
|
||||
func LP5EncodeTCKMin(memAttribs *LP5MemAttributes) byte {
|
||||
return convPsToMtbByte(memAttribs.TCKMinPs)
|
||||
}
|
||||
|
||||
func LP5EncodeTCKMinFineOffset(memAttribs *LP5MemAttributes) byte {
|
||||
return convPsToFtbByte(memAttribs.TCKMinPs)
|
||||
}
|
||||
|
||||
func LP5EncodeTAAMin(memAttribs *LP5MemAttributes) byte {
|
||||
return convPsToMtbByte(memAttribs.TAAMinPs)
|
||||
}
|
||||
|
||||
func LP5EncodeTAAMinFineOffset(memAttribs *LP5MemAttributes) byte {
|
||||
return convPsToFtbByte(memAttribs.TAAMinPs)
|
||||
}
|
||||
|
||||
func LP5EncodeTRCDMin(memAttribs *LP5MemAttributes) byte {
|
||||
return convNsToMtbByte(memAttribs.TRCDMinNs)
|
||||
}
|
||||
|
||||
func LP5EncodeTRCDMinFineOffset(memAttribs *LP5MemAttributes) byte {
|
||||
return convNsToFtbByte(memAttribs.TRCDMinNs)
|
||||
}
|
||||
|
||||
func LP5EncodeTRPABMin(memAttribs *LP5MemAttributes) byte {
|
||||
return convNsToMtbByte(memAttribs.TRPABMinNs)
|
||||
}
|
||||
|
||||
func LP5EncodeTRPABMinFineOffset(memAttribs *LP5MemAttributes) byte {
|
||||
return convNsToFtbByte(memAttribs.TRPABMinNs)
|
||||
}
|
||||
|
||||
func LP5EncodeTRPPBMin(memAttribs *LP5MemAttributes) byte {
|
||||
return convNsToMtbByte(memAttribs.TRPPBMinNs)
|
||||
}
|
||||
|
||||
func LP5EncodeTRPPBMinFineOffset(memAttribs *LP5MemAttributes) byte {
|
||||
return convNsToFtbByte(memAttribs.TRPPBMinNs)
|
||||
}
|
||||
|
||||
func LP5EncodeTRFCABMinMsb(memAttribs *LP5MemAttributes) byte {
|
||||
return byte((convNsToMtb(memAttribs.TRFCABNs) >> 8) & 0xff)
|
||||
}
|
||||
|
||||
func LP5EncodeTRFCABMinLsb(memAttribs *LP5MemAttributes) byte {
|
||||
return byte(convNsToMtb(memAttribs.TRFCABNs) & 0xff)
|
||||
}
|
||||
|
||||
func LP5EncodeTRFCPBMinMsb(memAttribs *LP5MemAttributes) byte {
|
||||
return byte((convNsToMtb(memAttribs.TRFCPBNs) >> 8) & 0xff)
|
||||
}
|
||||
|
||||
func LP5EncodeTRFCPBMinLsb(memAttribs *LP5MemAttributes) byte {
|
||||
return byte(convNsToMtb(memAttribs.TRFCPBNs) & 0xff)
|
||||
}
|
||||
|
||||
func LP5UpdateTCKMin(memAttribs *LP5MemAttributes) {
|
||||
if memAttribs.TCKMinPs == 0 {
|
||||
memAttribs.TCKMinPs = LP5SpeedMbpsToSPDEncoding[memAttribs.SpeedMbps].TCKMinPs
|
||||
}
|
||||
}
|
||||
|
||||
func LP5UpdateTAAMin(memAttribs *LP5MemAttributes) {
|
||||
if memAttribs.TAAMinPs == 0 {
|
||||
maxCAS := LP5SpeedMbpsToSPDEncoding[memAttribs.SpeedMbps].MaxCASLatency
|
||||
memAttribs.TAAMinPs = memAttribs.TCKMinPs * maxCAS
|
||||
}
|
||||
}
|
||||
|
||||
func LP5UpdateTRFCAB(memAttribs *LP5MemAttributes) {
|
||||
if memAttribs.TRFCABNs == 0 {
|
||||
memAttribs.TRFCABNs = LP5DensityGbToSPDEncoding[memAttribs.DensityPerDieGb].TRFCABNs
|
||||
}
|
||||
}
|
||||
|
||||
func LP5UpdateTRFCPB(memAttribs *LP5MemAttributes) {
|
||||
if memAttribs.TRFCPBNs == 0 {
|
||||
memAttribs.TRFCPBNs = LP5DensityGbToSPDEncoding[memAttribs.DensityPerDieGb].TRFCPBNs
|
||||
}
|
||||
}
|
||||
|
||||
func LP5UpdateTRCD(memAttribs *LP5MemAttributes) {
|
||||
if memAttribs.TRCDMinNs == 0 {
|
||||
/* Table 372 from JESD209-5B */
|
||||
memAttribs.TRCDMinNs = 18
|
||||
}
|
||||
}
|
||||
|
||||
func LP5UpdateTRPAB(memAttribs *LP5MemAttributes) {
|
||||
if memAttribs.TRPABMinNs == 0 {
|
||||
/* Table 372 from JESD209-5B */
|
||||
memAttribs.TRPABMinNs = 21
|
||||
}
|
||||
}
|
||||
|
||||
func LP5UpdateTRPPB(memAttribs *LP5MemAttributes) {
|
||||
if memAttribs.TRPPBMinNs == 0 {
|
||||
/* Table 372 from JESD209-5B */
|
||||
memAttribs.TRPPBMinNs = 18
|
||||
}
|
||||
}
|
||||
|
||||
func lp5UpdateMemoryAttributes(memAttribs *LP5MemAttributes) {
|
||||
LP5UpdateTCKMin(memAttribs)
|
||||
LP5UpdateTAAMin(memAttribs)
|
||||
LP5UpdateTRFCAB(memAttribs)
|
||||
LP5UpdateTRFCPB(memAttribs)
|
||||
LP5UpdateTRCD(memAttribs)
|
||||
LP5UpdateTRPAB(memAttribs)
|
||||
LP5UpdateTRPPB(memAttribs)
|
||||
}
|
||||
|
||||
func LP5ValidateDensity(density int) error {
|
||||
if _, ok := LP5DensityGbToSPDEncoding[density]; !ok {
|
||||
return fmt.Errorf("Incorrect density per die: %d Gb", density)
|
||||
}
|
||||
return nil
|
||||
}
|
||||
|
||||
func LP5ValidateDies(dies int) error {
|
||||
if dies != 2 && dies != 4 && dies != 8 {
|
||||
return fmt.Errorf("Incorrect dies: %d", dies)
|
||||
}
|
||||
return nil
|
||||
}
|
||||
|
||||
func LP5ValidateDataWidth(width int) error {
|
||||
if width != 8 && width != 16 {
|
||||
return fmt.Errorf("Incorrect bit width: %d", width)
|
||||
}
|
||||
return nil
|
||||
}
|
||||
|
||||
func LP5ValidateRanks(ranks int) error {
|
||||
if ranks != 1 && ranks != 2 {
|
||||
return fmt.Errorf("Incorrect ranks: %d", ranks)
|
||||
}
|
||||
return nil
|
||||
}
|
||||
|
||||
func LP5ValidateSpeed(speed int) error {
|
||||
if _, ok := LP5SpeedMbpsToSPDEncoding[speed]; !ok {
|
||||
return fmt.Errorf("Incorrect speed: %d Mbps", speed)
|
||||
}
|
||||
return nil
|
||||
}
|
||||
|
||||
func lp5ValidateMemPartAttributes(memAttribs *LP5MemAttributes) error {
|
||||
if err := LP5ValidateDensity(memAttribs.DensityPerDieGb); err != nil {
|
||||
return err
|
||||
}
|
||||
if err := LP5ValidateDies(memAttribs.DiesPerPackage); err != nil {
|
||||
return err
|
||||
}
|
||||
if err := LP5ValidateDataWidth(memAttribs.BitWidthPerChannel); err != nil {
|
||||
return err
|
||||
}
|
||||
if err := LP5ValidateRanks(memAttribs.RanksPerChannel); err != nil {
|
||||
return err
|
||||
}
|
||||
if err := LP5ValidateSpeed(memAttribs.SpeedMbps); err != nil {
|
||||
return err
|
||||
}
|
||||
|
||||
return nil
|
||||
}
|
||||
|
||||
func LP5IsManufacturerPartNumberByte(index int) bool {
|
||||
if index >= LP5SPDIndexManufacturerPartNumberStartByte &&
|
||||
index <= LP5SPDIndexManufacturerPartNumberEndByte {
|
||||
return true
|
||||
}
|
||||
return false
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------------------------ */
|
||||
/* Interface Functions */
|
||||
/* ------------------------------------------------------------------------------------------ */
|
||||
|
||||
func (lp5) getSetMap() map[int][]int {
|
||||
return LP5PlatformSetMap
|
||||
}
|
||||
|
||||
func (lp5) addNewPart(name string, attribs interface{}) error {
|
||||
var lp5Attributes LP5MemAttributes
|
||||
eByte, err := json.Marshal(attribs)
|
||||
if err != nil {
|
||||
return err
|
||||
}
|
||||
|
||||
if err := json.Unmarshal(eByte, &lp5Attributes); err != nil {
|
||||
return err
|
||||
}
|
||||
|
||||
if err := lp5ValidateMemPartAttributes(&lp5Attributes); err != nil {
|
||||
return err
|
||||
}
|
||||
|
||||
LP5PartAttributeMap[name] = lp5Attributes
|
||||
return nil
|
||||
}
|
||||
|
||||
func (lp5) getSPDAttribs(name string, set int) (interface{}, error) {
|
||||
lp5Attributes := LP5PartAttributeMap[name]
|
||||
|
||||
LP5CurrSet = set
|
||||
|
||||
lp5UpdateMemoryAttributes(&lp5Attributes)
|
||||
|
||||
return lp5Attributes, nil
|
||||
}
|
||||
|
||||
func (lp5) getSPDLen() int {
|
||||
return 512
|
||||
}
|
||||
|
||||
func (lp5) getSPDByte(index int, attribs interface{}) byte {
|
||||
e, ok := LP5SPDAttribTable[index]
|
||||
if !ok {
|
||||
if LP5IsManufacturerPartNumberByte(index) {
|
||||
return LP5SPDValueManufacturerPartNumberBlank
|
||||
}
|
||||
return 0x00
|
||||
}
|
||||
|
||||
if e.getVal != nil {
|
||||
var lp5Attribs LP5MemAttributes
|
||||
lp5Attribs = attribs.(LP5MemAttributes)
|
||||
return e.getVal(&lp5Attribs)
|
||||
}
|
||||
|
||||
return e.constVal
|
||||
}
|
||||
|
|
@ -65,6 +65,12 @@ var platformNames = map[int]string{
|
|||
PlatformCZN: "CZN",
|
||||
}
|
||||
|
||||
var memTechMap = map[string]memTech{
|
||||
"lp4x": lp4x{},
|
||||
"ddr4": ddr4{},
|
||||
"lp5": lp5{},
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------------------------ */
|
||||
/* Conversion Helper Functions */
|
||||
/* ------------------------------------------------------------------------------------------ */
|
||||
|
|
@ -211,7 +217,9 @@ func usage() {
|
|||
fmt.Printf("\nUsage: %s <mem_parts_list_json> <mem_technology>\n\n", os.Args[0])
|
||||
fmt.Printf(" where,\n")
|
||||
fmt.Printf(" mem_parts_list_json = JSON File containing list of memory parts and attributes\n")
|
||||
fmt.Printf(" mem_technology = Memory technology -- one of lp4x, ddr4\n\n\n")
|
||||
fmt.Printf(" mem_technology = Memory technology for which to generate SPDs\n")
|
||||
fmt.Printf(" supported technologies: %v\n\n\n",
|
||||
reflect.ValueOf(memTechMap).MapKeys())
|
||||
}
|
||||
|
||||
func main() {
|
||||
|
|
@ -223,11 +231,8 @@ func main() {
|
|||
var t memTech
|
||||
memPartsFilePath, memTechnology := os.Args[1], os.Args[2]
|
||||
|
||||
if strings.ToUpper(memTechnology) == "LP4X" {
|
||||
t = lp4x{}
|
||||
} else if strings.ToUpper(memTechnology) == "DDR4" {
|
||||
t = ddr4{}
|
||||
} else {
|
||||
t, ok := memTechMap[strings.ToLower(memTechnology)]
|
||||
if !ok {
|
||||
log.Fatal("Unsupported memory technology ", memTechnology)
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue