intel: Do not hardcode the position of mrc.cache

The reason for hardcoding the position of the MRC cache was to satisfy
the alignment to the erase size of the flash chip. Hardcoding is no
longer needed, as we can specify alignment directly. In the long term,
the MRC cache will have to move to FMAP, but for now, we reduce
fragmentation in CBFS.

Note that soc/intel/common hardcoding of mrc.cache is not removed, as
the mrc cache implementation there does not use CBFS to find the cache
region, and needs a hardcoded address.

Change-Id: I5b9fc1ba58bb484c7b5f687368172d9ebe625bfd
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11527
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/drivers/intel/fsp1_0/Kconfig

@@ -82,17 +82,6 @@ config MRC_CACHE_SIZE
 	  should be a full sector of the flash ROM chip and nothing else should
 	  be included in CBFS in any sector that the fast boot cache data is in.
 
-config MRC_CACHE_LOC
-	hex "Fast Boot Data Cache location in CBFS"
-	default 0xfff50000
-	depends on ENABLE_MRC_CACHE
-	help
-	  The location in CBFS for the MRC data to be cached.
-
-	  WARNING: This should be on a sector boundary of the BIOS ROM chip
-	  and nothing else should be included in that sector, or IT WILL BE
-	  ERASED.
-
 config VIRTUAL_ROM_SIZE
 	hex "Virtual ROM Size"
 	default ROM_SIZE

src/drivers/intel/fsp1_0/Makefile.inc

@@ -42,6 +42,6 @@ $(obj)/mrc.cache:
 
 cbfs-files-y += mrc.cache
 mrc.cache-file := $(obj)/mrc.cache
-mrc.cache-position := $(CONFIG_MRC_CACHE_LOC)
+mrc.cache-align := 0x10000
 mrc.cache-type := mrc_cache
 endif

src/mainboard/intel/bakersport_fsp/Kconfig

@@ -50,11 +50,6 @@ config FSP_FILE
 	string
 	default "../intel/fsp/baytrail/BAYTRAIL_FSP_ECC.fd" if BOARD_INTEL_BAKERSPORT_FSP
 
-config MRC_CACHE_LOC
-	hex
-	default 0xfff80000
-	depends on ENABLE_FSP_FAST_BOOT
-
 config CBFS_SIZE
 	hex
 	default 0x00200000

src/mainboard/intel/bayleybay_fsp/Kconfig

@@ -50,11 +50,6 @@ config FSP_FILE
 	string
 	default "../intel/fsp/baytrail/BAYTRAIL_FSP.fd"
 
-config MRC_CACHE_LOC
-	hex
-	default 0xfff80000
-	depends on ENABLE_FSP_FAST_BOOT
-
 config CBFS_SIZE
 	hex
 	default 0x00200000

src/mainboard/intel/minnowmax/Kconfig

@@ -49,11 +49,6 @@ config FSP_FILE
 	string
 	default "../intel/fsp/baytrail/BAYTRAIL_FSP.fd"
 
-config MRC_CACHE_LOC
-	hex
-	default 0xfff80000
-	depends on ENABLE_FSP_FAST_BOOT
-
 config CBFS_SIZE
 	hex
 	default 0x00300000

src/mainboard/siemens/mc_tcu3/Kconfig

@@ -49,11 +49,6 @@ config CACHE_ROM_SIZE_OVERRIDE
 	hex
 	default 0x1000000
 
-config MRC_CACHE_LOC
-	hex
-	default 0xfff80000
-	depends on ENABLE_FSP_FAST_BOOT
-
 config CBFS_SIZE
 	hex
 	default 0x00e00000

src/northbridge/intel/haswell/Makefile.inc

@@ -50,7 +50,7 @@ $(obj)/mrc.cache: $(obj)/config.h
 
 cbfs-files-y += mrc.cache
 mrc.cache-file := $(obj)/mrc.cache
-mrc.cache-position := 0xfffe0000
+mrc.cache-align := 0x10000
 mrc.cache-type := mrc_cache
 endif
 

src/northbridge/intel/nehalem/Makefile.inc

@@ -42,7 +42,7 @@ $(obj)/mrc.cache:
 
 cbfs-files-y += mrc.cache
 mrc.cache-file := $(obj)/mrc.cache
-mrc.cache-position := 0xfffe0000
+mrc.cache-align := 0x10000
 mrc.cache-type := mrc_cache
 
 endif

src/northbridge/intel/sandybridge/Makefile.inc

@@ -59,11 +59,7 @@ $(obj)/mrc.cache: $(obj)/config.h
 
 cbfs-files-y += mrc.cache
 mrc.cache-file := $(obj)/mrc.cache
-mrc-cache-position-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) := 0xfffd0000
-mrc-cache-position-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) := 0xfffd0000
-mrc-cache-position-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) := 0xfffe0000
-mrc-cache-position-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE) := 0xfffe0000
-mrc.cache-position := $(mrc-cache-position-y)
+mrc.cache-align := 0x10000
 mrc.cache-type := mrc_cache
 endif