mb/google/brya: Disable PCH USB2 phy power gating for felwinter
The patch disables PCH USB2 Phy power gating to prevent possible display flicker issue for felwinter board. Please refer Intel doc#723158 for more information. BUG=b:221461379, b:226020977 TEST=Verify the build for felwinter board Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I25033ea218fa3154eb99af6be43c4198f4db3bcb Reviewed-on: https://review.coreboot.org/c/coreboot/+/63294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
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@ -44,6 +44,10 @@ chip soc/intel/alderlake
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[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
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[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
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}"
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}"
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# As per Intel Advisory doc#723158, the change is required to prevent possible
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# display flickering issue.
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register "usb2_phy_sus_pg_disable" = "1"
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# Intel Common SoC Config
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# Intel Common SoC Config
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#+-------------------+---------------------------+
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#+-------------------+---------------------------+
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#| Field | Value |
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#| Field | Value |
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