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superio/winbond/w83627thg: Depreciate romstage component 

Depreciate the model specific early_serial.c romstage component for this
Super I/O in favor of the recent generic winbond romstage framework.

Change-Id: I22775dc9b6341c8994d21591b7176abe4dd99911
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5724
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
This commit is contained in:
Edward O'Callaghan 2014-05-13 23:29:22 +10:00 committed by Idwer Vollering
parent 92da206532
commit 2c55b70d1a
3 changed files with 18 additions and 54 deletions
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22
src/mainboard/kontron/986lcd-m/romstage.c
View File

@ -76,6 +76,20 @@ static void ich7_enable_lpc(void)
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301);
}
/* TODO: superio code should really not be in mainboard */
static void pnp_enter_func_mode(device_t dev)
{
u16 port = dev >> 8;
outb(0x87, port);
outb(0x87, port);
}
static void pnp_exit_func_mode(device_t dev)
{
u16 port = dev >> 8;
outb(0xaa, port);
}
/* This box has two superios, so enabling serial becomes slightly excessive.
* We disable a lot of stuff to make sure that there are no conflicts between
* the two. Also set up the GPIOs from the beginning. This is the "no schematic
@ -86,7 +100,7 @@ static void early_superio_config_w83627thg(void)
device_t dev;
dev=PNP_DEV(0x2e, W83627THG_SP1);
pnp_enter_ext_func_mode(dev);
pnp_enter_func_mode(dev);
pnp_write_config(dev, 0x24, 0xc6); // PNPCSV
@ -148,10 +162,10 @@ static void early_superio_config_w83627thg(void)
pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00);
pnp_set_enable(dev, 1);
pnp_exit_ext_func_mode(dev);
pnp_exit_func_mode(dev);
dev=PNP_DEV(0x4e, W83627THG_SP1);
pnp_enter_ext_func_mode(dev);
pnp_enter_func_mode(dev);
pnp_set_logical_device(dev); // Set COM3 to sane non-conflicting values
pnp_set_enable(dev, 0);
@ -180,7 +194,7 @@ static void early_superio_config_w83627thg(void)
pnp_set_iobase(dev, PNP_IDX_IO0, 0x00);
pnp_set_iobase(dev, PNP_IDX_IO1, 0x00);
pnp_exit_ext_func_mode(dev);
pnp_exit_func_mode(dev);
}
static void rcba_config(void)

1
src/superio/winbond/w83627thg/Makefile.inc
View File

@ -20,5 +20,4 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
romstage-$(CONFIG_SUPERIO_WINBOND_W83627THG) += early_serial.c
ramstage-$(CONFIG_SUPERIO_WINBOND_W83627THG) += superio.c

49
src/superio/winbond/w83627thg/early_serial.c
View File

@ -1,49 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2000 AG Electronics Ltd.
* Copyright (C) 2003-2004 Linux Networx
* Copyright (C) 2004 Tyan
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/io.h>
#include <device/pnp.h>
#include "w83627thg.h"
void pnp_enter_ext_func_mode(device_t dev)
{
u16 port = dev >> 8;
outb(0x87, port);
outb(0x87, port);
}
void pnp_exit_ext_func_mode(device_t dev)
{
u16 port = dev >> 8;
outb(0xaa, port);
}
#ifndef __ROMCC__
void w83627thg_set_clksel_48(device_t dev) {
u8 reg8;
pnp_enter_ext_func_mode(dev);
reg8 = pnp_read_config(dev, 0x24);
reg8 |= (1 << 6); /* Set CLKSEL (clock input on pin 1) to 48MHz. */
pnp_write_config(dev, 0x24, reg8);
pnp_exit_ext_func_mode(dev);
}
#endif