superio/winbond/w83627thg: Depreciate romstage component
Depreciate the model specific early_serial.c romstage component for this Super I/O in favor of the recent generic winbond romstage framework. Change-Id: I22775dc9b6341c8994d21591b7176abe4dd99911 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5724 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
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@ -76,6 +76,20 @@ static void ich7_enable_lpc(void)
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pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301);
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pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301);
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}
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}
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/* TODO: superio code should really not be in mainboard */
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static void pnp_enter_func_mode(device_t dev)
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{
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u16 port = dev >> 8;
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outb(0x87, port);
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outb(0x87, port);
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}
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static void pnp_exit_func_mode(device_t dev)
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{
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u16 port = dev >> 8;
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outb(0xaa, port);
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}
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/* This box has two superios, so enabling serial becomes slightly excessive.
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/* This box has two superios, so enabling serial becomes slightly excessive.
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* We disable a lot of stuff to make sure that there are no conflicts between
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* We disable a lot of stuff to make sure that there are no conflicts between
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* the two. Also set up the GPIOs from the beginning. This is the "no schematic
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* the two. Also set up the GPIOs from the beginning. This is the "no schematic
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@ -86,7 +100,7 @@ static void early_superio_config_w83627thg(void)
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device_t dev;
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device_t dev;
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dev=PNP_DEV(0x2e, W83627THG_SP1);
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dev=PNP_DEV(0x2e, W83627THG_SP1);
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pnp_enter_ext_func_mode(dev);
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pnp_enter_func_mode(dev);
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pnp_write_config(dev, 0x24, 0xc6); // PNPCSV
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pnp_write_config(dev, 0x24, 0xc6); // PNPCSV
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@ -148,10 +162,10 @@ static void early_superio_config_w83627thg(void)
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pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00);
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pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00);
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pnp_set_enable(dev, 1);
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pnp_set_enable(dev, 1);
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pnp_exit_ext_func_mode(dev);
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pnp_exit_func_mode(dev);
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dev=PNP_DEV(0x4e, W83627THG_SP1);
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dev=PNP_DEV(0x4e, W83627THG_SP1);
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pnp_enter_ext_func_mode(dev);
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pnp_enter_func_mode(dev);
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pnp_set_logical_device(dev); // Set COM3 to sane non-conflicting values
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pnp_set_logical_device(dev); // Set COM3 to sane non-conflicting values
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pnp_set_enable(dev, 0);
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pnp_set_enable(dev, 0);
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@ -180,7 +194,7 @@ static void early_superio_config_w83627thg(void)
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pnp_set_iobase(dev, PNP_IDX_IO0, 0x00);
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pnp_set_iobase(dev, PNP_IDX_IO0, 0x00);
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pnp_set_iobase(dev, PNP_IDX_IO1, 0x00);
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pnp_set_iobase(dev, PNP_IDX_IO1, 0x00);
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pnp_exit_ext_func_mode(dev);
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pnp_exit_func_mode(dev);
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}
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}
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static void rcba_config(void)
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static void rcba_config(void)
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@ -20,5 +20,4 @@
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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##
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romstage-$(CONFIG_SUPERIO_WINBOND_W83627THG) += early_serial.c
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ramstage-$(CONFIG_SUPERIO_WINBOND_W83627THG) += superio.c
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ramstage-$(CONFIG_SUPERIO_WINBOND_W83627THG) += superio.c
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@ -1,49 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2000 AG Electronics Ltd.
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* Copyright (C) 2003-2004 Linux Networx
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* Copyright (C) 2004 Tyan
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/io.h>
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#include <device/pnp.h>
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#include "w83627thg.h"
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void pnp_enter_ext_func_mode(device_t dev)
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{
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u16 port = dev >> 8;
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outb(0x87, port);
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outb(0x87, port);
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}
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void pnp_exit_ext_func_mode(device_t dev)
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{
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u16 port = dev >> 8;
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outb(0xaa, port);
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}
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#ifndef __ROMCC__
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void w83627thg_set_clksel_48(device_t dev) {
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u8 reg8;
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pnp_enter_ext_func_mode(dev);
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reg8 = pnp_read_config(dev, 0x24);
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reg8 |= (1 << 6); /* Set CLKSEL (clock input on pin 1) to 48MHz. */
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pnp_write_config(dev, 0x24, reg8);
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pnp_exit_ext_func_mode(dev);
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}
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#endif
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