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soc/intel/tigerlake: Remove polling for Link Active Status at resume 

Tigerlake TBT only has SW CM support. The polling for "LA == 1" is not
applicable for SW CM platform at the resume sequence. This change
removes the pollng for "LA == 1" to improve resume performance.

BUG=b:177519081
TEST=Boot to kernel and validated s0ix on Voxel board.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I886001f71bf893dc7eda98403fa4e1a3de6b958e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
John Zhao 2021-02-16 09:22:47 -08:00 committed by Tim Wawrzynczak
parent 83e6c15b0e
commit 2c7842407a
1 changed files with 0 additions and 12 deletions
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12
src/soc/intel/tigerlake/acpi/tcss_pcierp.asl
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@ -144,18 +144,6 @@ Method (D3CX, 0, Serialized)
Local1 = L23R
}
STAT = 0x1
/* Wait for LA = 1 */
Local0 = 0
Local1 = LASX
While (Local1 == 0) {
If (Local0 > 20) {
Break
}
Sleep(5)
Local0++
Local1 = LASX
}
}
/*