Documentation/releases: Update 4.15 release notes
Update details for upcoming 4.15 release Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Change-Id: I4517f7c17ce5788c82a1eafb1589e39b1ce403ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/58422 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Jason Glenesk
Patrick Georgi
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Upcoming release - coreboot 4.15
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================================
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The 4.15 release is planned for October 2021.
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The 4.15 release is planned for November 1st, 2021.
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Update this document with changes that should be in the release notes.
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Since 4.14 there have been more than 2448 new commits by more than 219 developers.
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Of these, over 73 contributed to coreboot for the first time.
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* Please use Markdown.
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* See the past few release notes for the general format.
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* The chip and board additions and removals will be updated right
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before the release, so those do not need to be added.
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Welcome to the project!
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Thank you to all the developers who continue to make coreboot the
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great open source firmware project that it is.
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New mainboards
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--------------
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* Asus p8h61-m_pro_cm6630
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* Asus p8h77-v
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* Asus p8z77-v
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* Google nipperkin
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* Lenovo w541
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* Siemens mc_ehl
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* SuperMicro x9sae
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* System76 addw1
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* System76 darp6
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* System76 darp7
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* System76 galp4
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* System76 galp5
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* System76 lemp10
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Removed mainboards
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------------------
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* Google Mancomb
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Deprecations and incompatible changes
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-------------------------------------
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### COREBOOTPAYLOAD option
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Drop the deprecated COREBOOTPAYLOAD option, and replace it with MrChromebox's
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updated UefiPayloadPkg option. Simplify the Kconfig options to make it easier
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to build from upstream edk2 master. Drop the TIANOCORE_USE_8254_TIMER Kconfig
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option since it applied only to CorebootPayloadPkg. Clean up the Makefile now
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that we're only building from a single Tianocore package/target.
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### Remove old lp4x and ddr4 versions of spd_tools
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The migration to the new unified version of spd_tools is complete, so
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the old lp4x and ddr4 versions can be removed.
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### Remove AMD PI 00630F01
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No board currently uses AMD PI 00630F01 so remove it.
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Significant changes
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-------------------
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@ -37,4 +80,35 @@ payload)
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Unit testing of libpayload is now possible in the same fashion as in the main
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coreboot tree.
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### Add significant changes here
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### Introduce new method for accessing cpu_info
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There is currently a fundamental flaw in the current cpu_info()
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implementation. It assumes that current stack is CONFIG_STACK_SIZE
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aligned. This assumption breaks down when performing SMM relocation.
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The first step in performing SMM relocation is changing the SMBASE. This
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is accomplished by installing the smmstub at 0x00038000, which is the
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default SMM entry point. The stub is configured to set up a new stack
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with the size of 1 KiB (CONFIG_SMM_STUB_STACK_SIZE), and an entry point
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of smm_do_relocation located in RAMSTAGE RAM.
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This means that when smm_do_relocation is executed, it is running in SMM
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with a different sized stack. When cpu_info() gets called it will be
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using CONFIG_STACK_SIZE to calculate the location of the cpu_info
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struct. This results in reading random memory. Since cpu_info() has to
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run in multiple environments, we can't use a compile time constant to
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locate the cpu_info struct.
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This CL introduces a new way of locating cpu_info. It uses a per-cpu
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segment descriptor that points to a per-cpu segment that is allocated on
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the stack. By using a segment descriptor to point to the per-cpu data,
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we no longer need to calculate the location of the cpu_info struct. This
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has the following advantages:
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* Stacks no longer need to be CONFIG_STACK_SIZE aligned.
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* Accessing an unconfigured segment will result in an exception. This
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ensures no one can call cpu_info() from an unsupported environment.
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* Segment selectors are cleared when entering SMM and restored when
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leaving SMM.
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* There is a 1:1 mapping between cpu and cpu_info. When using
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COOP_MULTITASKING, a new cpu_info is currently allocated at the top of
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each thread's stack. This no longer needs to happen.
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