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mb/siemens/{mc_apl1,...,mc_apl5}: Fix GPIO settings 

Correct all GPIOs with reference to the Apollo Lake SoC EDS Vol 4
revision 2.4 chapter 10.1.2.3 List of Pins that are GPIOs but cannot be
used in Function 0 (GPIO) mode.

In additional, set an internal pull to any GPI that does not have an
external resistor so that the input is not in an undefined state.

Change-Id: Ia8fe457eddbed0f4ee6bff9ef9dd7a92545be40b
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
This commit is contained in:
Mario Scheithauer 2019-07-17 10:35:00 +02:00 committed by Werner Zeh
parent 7815c074b4
commit 2c7d184885
4 changed files with 23 additions and 23 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c
View File

@ -47,12 +47,12 @@ static const struct pad_config gpio_table[] = {
/* SDIO -- unused */
PAD_CFG_GPI(GPIO_166, DN_20K, DEEP), /* SDIO_CLK */
PAD_CFG_GPI(GPIO_167, NONE, DEEP), /* SDIO_D0 */
PAD_CFG_GPI(GPIO_167, DN_20K, DEEP), /* SDIO_D0 */
/* Configure SDIO to enable power gating. */
PAD_CFG_NF(GPIO_168, UP_20K, DEEP, NF1), /* SDIO_D1 */
PAD_CFG_GPI(GPIO_169, NONE, DEEP), /* SDIO_D2 */
PAD_CFG_GPI(GPIO_170, NONE, DEEP), /* SDIO_D3 */
PAD_CFG_GPI(GPIO_171, NONE, DEEP), /* SDIO_CMD */
PAD_CFG_GPI(GPIO_169, DN_20K, DEEP), /* SDIO_D2 */
PAD_CFG_GPI(GPIO_170, DN_20K, DEEP), /* SDIO_D3 */
PAD_CFG_GPI(GPIO_171, DN_20K, DEEP), /* SDIO_CMD */
/* SDCARD */
/* Pull down clock by 20K. */
@ -135,7 +135,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(OSC_CLK_OUT_4, DN_20K, DEEP),
/* PMU Signals */
PAD_CFG_GPI(PMU_AC_PRESENT, NONE, DEEP), /* PMU_AC_PRESENT */
PAD_CFG_GPI(PMU_AC_PRESENT, DN_20K, DEEP), /* PMU_AC_PRESENT */
PAD_CFG_NF(PMU_BATLOW_B, UP_20K, DEEP, NF1), /* PMU_BATLOW_N */
PAD_CFG_NF(PMU_PLTRST_B, NONE, DEEP, NF1), /* PMU_PLTRST_N */
PAD_CFG_NF(PMU_PWRBTN_B, NONE, DEEP, NF1), /* PMU_PWRBTN_N */
@ -173,7 +173,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(GPIO_198, DN_20K, DEEP), /* PNL1_BKLTCTL */
/* DDI[0:1]_HPD -- unused */
PAD_CFG_GPI(GPIO_199, NONE, DEEP), /* XHPD_DP */
PAD_CFG_GPI(GPIO_199, DN_20K, DEEP), /* XHPD_DP */
PAD_CFG_GPI(GPIO_200, DN_20K, DEEP), /* unused */
/* MDSI signals -- unused */
@ -193,7 +193,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(PMC_SPI_CLK, DN_20K, DEEP),
/* PMIC Signals unused signals related to an old PMIC interface. */
PAD_CFG_GPO(PMIC_PWRGOOD, 1, DEEP), /* PMIC_PWRGOOD */
PAD_CFG_NF(PMIC_PWRGOOD, UP_20K, DEEP, NF1), /* PMIC_PWRGOOD */
PAD_CFG_GPI(PMIC_RESET_B, DN_20K, DEEP), /* PMIC_RESET_B */
PAD_CFG_TERM_GPO(GPIO_213, 0, DN_20K, DEEP), /* NFC_OUT_RESERVE */
PAD_CFG_TERM_GPO(GPIO_214, 0, DN_20K, DEEP), /* NFC_EN */

6
src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c
View File

@ -123,9 +123,9 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_133, UP_1K, DEEP, NF1, Tx1RxDCRx1,
MASK),
/* Not connected */
PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_134, NONE, DEEP, Tx0RxDCRx0, MASK),
PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_134, UP_20K, DEEP, Tx0RxDCRx0, MASK),
/* Not connected */
PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_135, NONE, DEEP, Tx0RxDCRx0, MASK),
PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_135, UP_20K, DEEP, Tx0RxDCRx0, MASK),
/* GPIO_PWRBTN# */
PAD_CFG_GPI_SCI_IOS(GPIO_136, UP_20K, DEEP, EDGE_SINGLE, INVERT,
TxDRxE, SAME),
@ -276,7 +276,7 @@ static const struct pad_config gpio_table[] = {
SAME),
/* Not connected */
PAD_CFG_GPO_GPIO_DRIVER(PMIC_PWRGOOD, 1, DEEP, UP_1K),
PAD_CFG_NF(PMIC_PWRGOOD, UP_20K, DEEP, NF1),
PAD_CFG_GPO_GPIO_DRIVER(GPIO_214, 1, DEEP, DN_20K),
PAD_CFG_GPO_GPIO_DRIVER(GPIO_215, 1, DEEP, DN_20K),
/* THERMTRIP_1V8# - Connected to CPLD */

22
src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c
View File

@ -178,7 +178,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(PMC_SPI_CLK, DN_20K, DEEP), /* unused */
/* PMIC Signals unused signals related to an old PMIC interface. */
PAD_CFG_GPI(PMIC_PWRGOOD, DN_20K, DEEP), /* PMIC_PWRGOOD */
PAD_CFG_NF(PMIC_PWRGOOD, DN_20K, DEEP, NF1), /* PMIC_PWRGOOD */
PAD_CFG_GPI(PMIC_RESET_B, DN_20K, DEEP), /* PMIC_RESET_B */
PAD_CFG_GPI(GPIO_213, UP_20K, DEEP), /* PMIC_SDWN_B */
PAD_CFG_GPI(GPIO_214, DN_20K, DEEP), /* PMIC_BCUDISW2 */
@ -318,16 +318,16 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(GPIO_73, DN_20K, DEEP), /* pin open */
/* no TAP controller pins available on SMARC of APL4 */
PAD_CFG_GPI(TCK, DN_20K, DEEP), /* pin open */
PAD_CFG_GPI(TRST_B, DN_20K, DEEP), /* pin open */
PAD_CFG_GPI(TMS, DN_20K, DEEP), /* pin open */
PAD_CFG_GPI(TDI, DN_20K, DEEP), /* pin open */
PAD_CFG_NF(TCK, DN_20K, DEEP, NF1), /* pin open */
PAD_CFG_NF(TRST_B, DN_20K, DEEP, NF1), /* pin open */
PAD_CFG_NF(TMS, DN_20K, DEEP, NF1), /* pin open */
PAD_CFG_NF(TDI, DN_20K, DEEP, NF1), /* pin open */
PAD_CFG_GPI(CX_PMODE, DN_20K, DEEP), /* pin open */
PAD_CFG_GPI(CX_PREQ_B, DN_20K, DEEP), /* pin open */
PAD_CFG_GPI(JTAGX, DN_20K, DEEP), /* pin open */
PAD_CFG_GPI(CX_PRDY_B, DN_20K, DEEP), /* pin open */
PAD_CFG_GPI(TDO, DN_20K, DEEP), /* pin open */
PAD_CFG_NF(CX_PMODE, DN_20K, DEEP, NF1), /* pin open */
PAD_CFG_NF(CX_PREQ_B, DN_20K, DEEP, NF1), /* pin open */
PAD_CFG_NF(JTAGX, DN_20K, DEEP, NF1), /* pin open */
PAD_CFG_NF(CX_PRDY_B, DN_20K, DEEP, NF1), /* pin open */
PAD_CFG_NF(TDO, DN_20K, DEEP, NF1), /* pin open */
/* GPIO_[216:219] described into EDS Vol1. */
PAD_CFG_GPO(CNV_BRI_DT, 0, DEEP), /* Disable eDP to LVDS bridge */
@ -335,7 +335,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(CNV_RGI_DT, DN_20K, DEEP), /* pin open */
/* Writing to following GPIO registers leads to 0xFFFF FFFF in CFG0/1 */
PAD_CFG_GPI(CNV_RGI_RSP, DN_20K, DEEP), /* pin open */
PAD_CFG_NF(CNV_RGI_RSP, DN_20K, DEEP, NF1), /* pin open */
/* Serial Voltage Identification */
PAD_CFG_NF(SVID0_ALERT_B, NONE, DEEP, NF1), /* SVID0_ALERT_B */

4
src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c
View File

@ -135,7 +135,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(OSC_CLK_OUT_4, DN_20K, DEEP),
/* PMU Signals */
PAD_CFG_GPI(PMU_AC_PRESENT, NONE, DEEP), /* PMU_AC_PRESENT */
PAD_CFG_GPI(PMU_AC_PRESENT, DN_20K, DEEP), /* PMU_AC_PRESENT */
PAD_CFG_NF(PMU_BATLOW_B, UP_20K, DEEP, NF1), /* PMU_BATLOW_N */
PAD_CFG_NF(PMU_PLTRST_B, NONE, DEEP, NF1), /* PMU_PLTRST_N */
PAD_CFG_NF(PMU_PWRBTN_B, NONE, DEEP, NF1), /* PMU_PWRBTN_N */
@ -193,7 +193,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(PMC_SPI_CLK, DN_20K, DEEP),
/* PMIC Signals unused signals related to an old PMIC interface. */
PAD_CFG_GPO(PMIC_PWRGOOD, 1, DEEP), /* PMIC_PWRGOOD */
PAD_CFG_NF(PMIC_PWRGOOD, UP_20K, DEEP, NF1), /* PMIC_PWRGOOD */
PAD_CFG_GPI(PMIC_RESET_B, DN_20K, DEEP), /* PMIC_RESET_B */
PAD_CFG_TERM_GPO(GPIO_213, 0, DN_20K, DEEP), /* NFC_OUT_RESERVE */
PAD_CFG_TERM_GPO(GPIO_214, 0, DN_20K, DEEP), /* NFC_EN */