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mb/google/volteer: Disable D3Cold for TCSS along with pass through mode

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The pass through mode (SW CM) RTD3 is not supported until QS platform.
D3Cold is needed to be disabled along with upstream TBT firmware
signed_TGL_HR_4C_A0_rev6_pre4_SW_CM_PM_support_ENG_VER_perst_check_fix.
This temporary patch will need to be reverted once PM RTD3 support is
validated on QS platform.

BUG=b:159050315
TEST=Verfiy PM S0ix along with upstream TBT firmware.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I98ed991e4185abf1f3168e33b099e0e97c9075f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42504
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Divya Sasidharan <divya.s.sasidharan@intel.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
John Zhao 2020-06-18 00:25:51 -07:00 committed by Patrick Georgi
parent 2dcca0f924
commit 2c807ff6fe
1 changed files with 1 additions and 1 deletions
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src/mainboard/google/volteer/variants/baseboard/devicetree.cb
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@ -159,7 +159,7 @@ chip soc/intel/tigerlake
# D3Hot and D3Cold for TCSS
register "TcssD3HotEnable" = "1"
register "TcssD3ColdEnable" = "1"
register "TcssD3ColdEnable" = "0"
# DP port
register "DdiPortAConfig" = "1" # eDP