soc/intel/braswell: Add USB2 phy setting override

Adapted from Chromium commit 9756af8.

Create hook function to override USB2 phy setting from board level.

Original-Change-Id: Ic736dd945f01cf9f24af4ce3bd3f2757abfdeb2e
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Keith Tzeng <keith.tzeng@quantatw.com>

Change-Id: If2ac687f6fc44e4c022a72eea7f08cb6385f0380
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/intel/braswell/chip.c

@@ -81,6 +81,10 @@ static void enable_dev(device_t dev)
 	}
 }
 
+__attribute__((weak)) void board_silicon_USB2_override(SILICON_INIT_UPD *params)
+{
+}
+
 void soc_silicon_init_params(SILICON_INIT_UPD *params)
 {
 	device_t dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC));
@@ -170,6 +174,7 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
 	params->I2C5Frequency = config->I2C5Frequency;
 	params->I2C6Frequency = config->I2C6Frequency;
 
+	board_silicon_USB2_override(params);
 }
 
 void soc_display_silicon_init_params(const SILICON_INIT_UPD *old,

src/soc/intel/braswell/include/soc/ramstage.h

@@ -101,6 +101,7 @@ void set_max_freq(void);
 void southcluster_enable_dev(device_t dev);
 void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index);
 int SocStepping(void);
+void board_silicon_USB2_override(SILICON_INIT_UPD *params);
 
 extern struct pci_operations soc_pci_ops;