soc/marvell/armada38x: Add generic support for armada38x
Skeleton for soc armada38x BUG=chrome-os-partner:47462 TEST=None BRANCH=tot Change-Id: I76f631ee6cdfc90c44727cb20aa960796bc785a5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e91cc19468325f005c6ac920bbe27a174c409727 Original-Change-Id: Iac5fc34df1ba18b4515029aa2fcff8f78a5df191 Original-Signed-off-by: Ruilin Hao <rlhao@marvell.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313179 Original-Commit-Ready: Kan Yan <kyan@google.com> Original-Tested-by: Kan Yan <kyan@google.com> Original-Reviewed-by: Kan Yan <kyan@google.com> Reviewed-on: https://review.coreboot.org/13110 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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config SOC_MARVELL_ARMADA38X
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bool
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default n
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select ARCH_BOOTBLOCK_ARMV7
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select ARCH_VERSTAGE_ARMV7
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select ARCH_ROMSTAGE_ARMV7
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select ARCH_RAMSTAGE_ARMV7
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select HAVE_UART_SPECIAL
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select BOOTBLOCK_CONSOLE
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select RETURN_FROM_VERSTAGE
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select BOOTBLOCK_CUSTOM
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select GENERIC_UDELAY
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if SOC_MARVELL_ARMADA38X
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config BOOTBLOCK_CPU_INIT
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string
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default "soc/marvell/armada38x/bootblock.c"
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help
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CPU/SoC-specific bootblock code. This is useful if the
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bootblock must load microcode or copy data from ROM before
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searching for the bootblock.
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config CONSOLE_SERIAL_UART_ADDRESS
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hex
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default 0xf1012000
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endif
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@ -0,0 +1,31 @@
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ifeq ($(CONFIG_SOC_MARVELL_ARMADA38X),y)
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bootblock-y += bootblock.c
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bootblock-y += bootblock_asm.S
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bootblock-y += monotonic_timer.c
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ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y)
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bootblock-$(CONFIG_DRIVERS_UART) += uart.c
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endif
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verstage-$(CONFIG_DRIVERS_UART) += uart.c
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verstage-y += monotonic_timer.c
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romstage-y += cbmem.c
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romstage-y += monotonic_timer.c
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romstage-$(CONFIG_DRIVERS_UART) += uart.c
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ramstage-y += cbmem.c
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ramstage-y += monotonic_timer.c
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ramstage-y += soc.c
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ramstage-$(CONFIG_DRIVERS_UART) += uart.c
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CPPFLAGS_common += -Isrc/soc/marvell/armada38x/include/
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BIN_HDR = 3rdparty/blobs/cpu/marvell/armada38x/bin_hdr.bin
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DOIMAGE = 3rdparty/blobs/cpu/marvell/armada38x/doimage
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$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
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@chmod a+x $(DOIMAGE)
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$(DOIMAGE) -T flash -D 0 -E 0 -G $(BIN_HDR) $< $@
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rm $<
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endif
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@ -0,0 +1,176 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2015 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <assert.h>
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#include <arch/io.h>
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#include <arch/cache.h>
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#include <arch/exception.h>
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#include <arch/hlt.h>
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#include <bootblock_common.h>
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#include <cbfs.h>
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#include <console/console.h>
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#include <delay.h>
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#include <arch/stages.h>
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#include <symbols.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include <soc/common.h>
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#define CLOCK_BIT_SATA23 BIT30
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#define CLOCK_BIT_PNC BIT29
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#define CLOCK_BIT_TDM BIT25
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#define CLOCK_BIT_CRYPTO0_GATE BIT23
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#define CLOCK_BIT_CRYPTO1_GATE BIT21
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#define CLOCK_BIT_CRYPTO1_Z BIT16
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#define CLOCK_BIT_SATA01 BIT15
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#define CLOCK_BIT_CRYPTO0_Z BIT14
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#define CLOCK_BIT_BM BIT13
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#define CLOCK_BIT_PCIE2 BIT6
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#define CLOCK_BIT_PCIE1 BIT5
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#define CLOCK_BIT_GBE0 BIT4
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#define CLOCK_BIT_GBE1 BIT3
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#define CLOCK_BIT_GBE2 BIT2
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#define CLOCK_BIT_AUDIO BIT0
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#define A38x_MPP0_7_OFFSET 0x18000
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#define A38x_MPP8_15_OFFSET 0x18004
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#define A38x_MPP16_23_OFFSET 0x18008
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#define A38x_MPP24_31_OFFSET 0x1800c
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#define A38x_MPP32_39_OFFSET 0x18010
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#define A38x_MPP40_47_OFFSET 0x18014
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#define A38x_MPP48_55_OFFSET 0x18018
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#define A38x_MPP56_63_OFFSET 0x1801c
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#define A38X_GPP_OUT_ENA_OFFSET_LOW 0x18104
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#define A38X_GPP_OUT_ENA_OFFSET_MID 0x18144
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#define A38X_GPP_OUT_VALUE_OFFSET_LOW 0x18100
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#define A38X_GPP_OUT_VALUE_OFFSET_MID 0x18140
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#define A38x_CUBE_BOARD_MPP0_7 0x00001111
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#define A38x_CUBE_BOARD_MPP8_15 0x46200000
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#define A38x_CUBE_BOARD_MPP16_23 0x00400444
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#define A38x_CUBE_BOARD_MPP24_31 0x00043300
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#define A38x_CUBE_BOARD_MPP32_39 0x44400000
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#define A38x_CUBE_BOARD_MPP40_47 0x00000004
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#define A38x_CUBE_BOARD_MPP48_55 0x00444444
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#define A38x_CUBE_BOARD_MPP56_63 0x00004444
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/* Set bit x to enable GPIO output mode for MPP x */
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#define A38x_CUBE_BOARD_0_GPP_OUT_ENA_LOW ~(BIT4 | BIT6)
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/* MID group is for MPP32 ~ MPP63 e.g BIT3 corresponds to MPP35 */
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#define A38x_CUBE_BOARD_0_GPP_OUT_ENA_MID ~(BIT3)
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#define A38x_CUSTOMER_BOARD_0_GPP_OUT_VAL_LOW (BIT4)
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/* MID group is for MPP32 ~ MPP63 e.g BIT3 corresponds to MPP35 */
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#define A38x_CUSTOMER_BOARD_0_GPP_OUT_VAL_MID (BIT3)
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#define A38X_POWER_MANAGEMENT_CLOCK_GATING_CONTROL 0x18220
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#define A38x_SOC_IO_ERR_CTRL_OFFSET 0x20200
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#define A38x_SOC_WIN_CTRL_OFFSET 0x20250
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#define A38x_SOC_WIN_BASE_OFFSET 0x20254
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#define A38x_CUBE_BOARD_SOC_IO_ERR_CTRL 0x00000000
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#define A38x_CUBE_BOARD_SOC_WIN_CTRL 0x1ff00001
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#define A38x_CUBE_BOARD_SOC_BASE_CTRL 0xe0000000
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#define DRAM_START ((uintptr_t)_dram / MiB)
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#define DRAM_SIZE (CONFIG_DRAM_SIZE_MB)
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/* DMA memory for drivers */
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#define DMA_START ((uintptr_t)_dma_coherent / MiB)
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#define DMA_SIZE (_dma_coherent_size / MiB)
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static void setup_pinmux(void)
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{
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/* Hard coded pin mux configuration */
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mrvl_reg_write(A38x_MPP0_7_OFFSET, A38x_CUBE_BOARD_MPP0_7);
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mrvl_reg_write(A38x_MPP8_15_OFFSET, A38x_CUBE_BOARD_MPP8_15);
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mrvl_reg_write(A38x_MPP16_23_OFFSET, A38x_CUBE_BOARD_MPP16_23);
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mrvl_reg_write(A38x_MPP24_31_OFFSET, A38x_CUBE_BOARD_MPP24_31);
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mrvl_reg_write(A38x_MPP32_39_OFFSET, A38x_CUBE_BOARD_MPP32_39);
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mrvl_reg_write(A38x_MPP40_47_OFFSET, A38x_CUBE_BOARD_MPP40_47);
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mrvl_reg_write(A38x_MPP48_55_OFFSET, A38x_CUBE_BOARD_MPP48_55);
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mrvl_reg_write(A38x_MPP56_63_OFFSET, A38x_CUBE_BOARD_MPP56_63);
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}
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static void setup_gpp_out_value(void)
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{
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mrvl_reg_write(
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A38X_GPP_OUT_VALUE_OFFSET_LOW,
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A38x_CUSTOMER_BOARD_0_GPP_OUT_VAL_LOW);
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mrvl_reg_write(
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A38X_GPP_OUT_VALUE_OFFSET_MID,
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A38x_CUSTOMER_BOARD_0_GPP_OUT_VAL_MID);
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}
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static void setup_gpp_out_enable(void)
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{
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mrvl_reg_write(
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A38X_GPP_OUT_ENA_OFFSET_LOW,
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A38x_CUBE_BOARD_0_GPP_OUT_ENA_LOW);
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mrvl_reg_write(
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A38X_GPP_OUT_ENA_OFFSET_MID,
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A38x_CUBE_BOARD_0_GPP_OUT_ENA_MID);
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}
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/* This function disable unused periperal clocks */
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static void setup_peripherals_clocks(void)
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{
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mrvl_reg_bit_reset(
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A38X_POWER_MANAGEMENT_CLOCK_GATING_CONTROL, (
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CLOCK_BIT_SATA23 | CLOCK_BIT_PNC | CLOCK_BIT_TDM |
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CLOCK_BIT_CRYPTO0_GATE | CLOCK_BIT_CRYPTO1_GATE |
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CLOCK_BIT_CRYPTO1_Z | CLOCK_BIT_SATA01 |
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CLOCK_BIT_CRYPTO0_Z | CLOCK_BIT_BM |
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CLOCK_BIT_PCIE2 | CLOCK_BIT_PCIE1 |
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CLOCK_BIT_GBE0 | CLOCK_BIT_GBE1 |
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CLOCK_BIT_GBE2 | CLOCK_BIT_AUDIO
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)
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);
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}
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static void setup_win_regs(void)
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{
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mrvl_reg_write(A38x_SOC_IO_ERR_CTRL_OFFSET,
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A38x_CUBE_BOARD_SOC_IO_ERR_CTRL);
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mrvl_reg_write(A38x_SOC_WIN_CTRL_OFFSET, A38x_CUBE_BOARD_SOC_WIN_CTRL);
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mrvl_reg_write(A38x_SOC_WIN_BASE_OFFSET, A38x_CUBE_BOARD_SOC_BASE_CTRL);
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}
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void main(void)
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{
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if (CONFIG_BOOTBLOCK_CONSOLE) {
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console_init();
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exception_init();
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}
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init_timer();
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/* enable mmu */
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mmu_init();
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mmu_config_range(0, 4096, DCACHE_OFF);
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mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK);
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mmu_config_range(DMA_START, DMA_SIZE, DCACHE_OFF);
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dcache_mmu_enable();
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bootblock_mainboard_init();
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setup_pinmux();
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setup_gpp_out_value();
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setup_gpp_out_enable();
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setup_win_regs();
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setup_peripherals_clocks();
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run_romstage();
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}
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@ -0,0 +1,123 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2015 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/asm.h>
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.arm
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/*
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* Just in case the maskrom or the vendor basic firmware passes on a
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* parameter when calling the bootblock, store it here for handling by C
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* code.
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*/
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.section .bss, "aw" @nobits
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.global maskrom_param
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.align 4
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maskrom_param:
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.word 0
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ENTRY(_start)
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/*
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* Set the cpu to System mode with IRQ and FIQ disabled. Prefetch/Data
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* aborts may happen early and crash before the abort handlers are
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* installed, but at least the problem will show up near the code that
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* causes it.
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*/
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msr cpsr_cxf, #0xdf
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bl _thumb_start
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ENDPROC(_start)
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.thumb
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ENTRY(_thumb_start)
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/* Preserve the maskrom passed value, if any */
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mov r10, r0
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/* Disable L2 Cache */
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ldr r1, =0x0
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ldr r0, =0xD0008100
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str r1, [r0]
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/* Disable windows that overlap with 0xF1000000 */
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/* By default, window #12 overlaps with 0xF1000000 */
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mov r1, #0
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ldr r0, =0xD00200B0
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str r1, [r0]
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/* Set Registers Base address. */
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ldr r1, =0xf1000000
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ldr r0, =0xD0020080
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str r1, [r0]
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/* Update SCU (peripheral) register Base address with
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* correct INTER_REG_BASE
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*/
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ldr r2, = 0xC000 /* SCU offset = 0xC000 */
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add r1, r1, r2 /* r1 = INTER_REG_BASE + SCU_OFFSET */
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mcr p15, 4, r1, c15, c0, 0 /* Write SCU base register */
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bl arm_init_caches
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/*
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* From Cortex-A Series Programmer's Guide:
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* Only CPU 0 performs initialization. Other CPUs go into WFI
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* to do this, first work out which CPU this is
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* this code typically is run before any other initialization step
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*/
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mrc p15, 0, r1, c0, c0, 5 @ Read Multiprocessor Affinity Register
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and r1, r1, #0x3 @ Extract CPU ID bits
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cmp r1, #0
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bne wait_for_interrupt @ If this is not core0, wait
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/*
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* Initialize the stack to a known value. This is used to check for
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* stack overflow later in the boot process.
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*/
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ldr r0, =_stack
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ldr r1, =_estack
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ldr r2, =0xdeadbeef
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init_stack_loop:
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str r2, [r0]
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add r0, #4
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cmp r0, r1
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bne init_stack_loop
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ldr r0, =_bss
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ldr r1, =_ebss
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mov r2, #0x00000000 /* prepare zero to clear BSS */
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clbss_l:
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str r2, [r0]
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add r0, #4
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cmp r0, r1
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bne clbss_l
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call_bootblock:
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/* Restore parameter passed in by maskrom/vendor firmware. */
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ldr r0, =maskrom_param
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str r10, [r0]
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/* Set stackpointer in internal RAM to call bootblock main() */
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ldr sp, =_estack
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ldr r0,=0x00000000
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/*
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* The current design of cpu_info places the struct at the top of the
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* stack. Free enough space to accommodate for that, but make sure it's
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* 8-byte aligned for ABI compliance.
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*/
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sub sp, sp, #16
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bl main
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wait_for_interrupt:
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wfi
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mov pc, lr @ back to my caller
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ENDPROC(_thumb_start)
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@ -0,0 +1,22 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2015 Google Inc.
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||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
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*/
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#include <cbmem.h>
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#include <soc/soc_services.h>
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void *cbmem_top(void)
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{
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return (void *)_memlayout_cbmem_top;
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}
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@ -0,0 +1,128 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2015 Marvell Inc.
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*
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
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#ifndef __SOC_MARVELL_ARMADA38X_COMMON_H_
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#define __SOC_MARVELL_ARMADA38X_COMMON_H_
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#include <types.h>
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#include <arch/io.h>
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#define INTER_REGS_BASE 0xF1000000
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#define MV_TRUE (1)
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#define MV_FALSE (0)
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/* The following is a list of Marvell status */
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#define MV_ERROR (-1)
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#define MV_OK (0)
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#define MV_FAIL (1)
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#define MV_BAD_VALUE (2)
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#define MV_OUT_OF_RANGE (3)
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#define MV_BAD_PARAM (4)
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#define MV_BAD_PTR (5)
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#define MV_BAD_SIZE (6)
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#define MV_BAD_STATE (7)
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#define MV_SET_ERROR (8)
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#define MV_GET_ERROR (9)
|
||||
#define MV_CREATE_ERROR (10)
|
||||
#define MV_NOT_FOUND (11)
|
||||
#define MV_NO_MORE (12)
|
||||
#define MV_NO_SUCH (13)
|
||||
#define MV_TIMEOUT (14)
|
||||
#define MV_NO_CHANGE (15)
|
||||
#define MV_NOT_SUPPORTED (16)
|
||||
#define MV_NOT_IMPLEMENTED (17)
|
||||
#define MV_NOT_INITIALIZED (18)
|
||||
#define MV_NO_RESOURCE (19)
|
||||
#define MV_FULL (20)
|
||||
#define MV_EMPTY (21)
|
||||
#define MV_INIT_ERROR (22)
|
||||
#define MV_HW_ERROR (23)
|
||||
#define MV_TX_ERROR (24)
|
||||
#define MV_RX_ERROR (25)
|
||||
#define MV_NOT_READY (26)
|
||||
#define MV_ALREADY_EXIST (27)
|
||||
#define MV_OUT_OF_CPU_MEM (28)
|
||||
#define MV_NOT_STARTED (29)
|
||||
#define MV_BUSY (30)
|
||||
#define MV_TERMINATE (31)
|
||||
#define MV_NOT_ALIGNED (32)
|
||||
#define MV_NOT_ALLOWED (33)
|
||||
#define MV_WRITE_PROTECT (34)
|
||||
#define MV_DROPPED (35)
|
||||
#define MV_STOLEN (36)
|
||||
#define MV_CONTINUE (37)
|
||||
#define MV_RETRY (38)
|
||||
|
||||
#define MV_INVALID (int)(-1)
|
||||
|
||||
#define MV_BOARD_TCLK_200MHZ 200000000
|
||||
#define MV_BOARD_TCLK_250MHZ 250000000
|
||||
|
||||
#define MPP_SAMPLE_AT_RESET (0x18600)
|
||||
|
||||
#define MV_6810_DEV_ID 0x6810
|
||||
|
||||
#define BIT0 0x00000001
|
||||
#define BIT1 0x00000002
|
||||
#define BIT2 0x00000004
|
||||
#define BIT3 0x00000008
|
||||
#define BIT4 0x00000010
|
||||
#define BIT5 0x00000020
|
||||
#define BIT6 0x00000040
|
||||
#define BIT7 0x00000080
|
||||
#define BIT8 0x00000100
|
||||
#define BIT9 0x00000200
|
||||
#define BIT10 0x00000400
|
||||
#define BIT11 0x00000800
|
||||
#define BIT12 0x00001000
|
||||
#define BIT13 0x00002000
|
||||
#define BIT14 0x00004000
|
||||
#define BIT15 0x00008000
|
||||
#define BIT16 0x00010000
|
||||
#define BIT17 0x00020000
|
||||
#define BIT18 0x00040000
|
||||
#define BIT19 0x00080000
|
||||
#define BIT20 0x00100000
|
||||
#define BIT21 0x00200000
|
||||
#define BIT22 0x00400000
|
||||
#define BIT23 0x00800000
|
||||
#define BIT24 0x01000000
|
||||
#define BIT25 0x02000000
|
||||
#define BIT26 0x04000000
|
||||
#define BIT27 0x08000000
|
||||
#define BIT28 0x10000000
|
||||
#define BIT29 0x20000000
|
||||
#define BIT30 0x40000000
|
||||
#define BIT31 0x80000000
|
||||
|
||||
static inline uint32_t mrvl_reg_read(uint32_t offset)
|
||||
{
|
||||
return read32((void *)(INTER_REGS_BASE + offset));
|
||||
}
|
||||
static inline void mrvl_reg_write(uint32_t offset, uint32_t val)
|
||||
{
|
||||
write32((void *)(INTER_REGS_BASE + offset), val);
|
||||
}
|
||||
static inline void mrvl_reg_bit_set(uint32_t offset, uint32_t bit_mask)
|
||||
{
|
||||
mrvl_reg_write(offset, (mrvl_reg_read(offset) | bit_mask));
|
||||
}
|
||||
static inline void mrvl_reg_bit_reset(uint32_t offset, uint32_t bit_mask)
|
||||
{
|
||||
mrvl_reg_write(offset, (mrvl_reg_read(offset) & (~bit_mask)));
|
||||
}
|
||||
|
||||
#endif // __SOC_MARVELL_ARMADA38X_COMMON_H__
|
|
@ -0,0 +1,34 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2015 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <memlayout.h>
|
||||
#include <arch/header.ld>
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
DRAM_START(0x00000000)
|
||||
BOOTBLOCK(0x00000000, 24K)
|
||||
RAMSTAGE(0x00800000, 128K)
|
||||
CBFS_CACHE(0x12006000, 80K)
|
||||
STACK(0x1201c000, 16K)
|
||||
|
||||
VERSTAGE(0x1202c000, 96K)
|
||||
ROMSTAGE(0x12044000, 96K)
|
||||
VBOOT2_WORK(0x1205c000, 16K)
|
||||
DMA_COHERENT(0x12100000, 2M)
|
||||
SYMBOL(memlayout_cbmem_top, 0x1F400000)
|
||||
TTB(0x1FF00000, 16K)
|
||||
TTB_SUBTABLES(0x1FF04000, 2K)
|
||||
}
|
|
@ -0,0 +1,23 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2015 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __SOC_MARVELL_ARMADA38X_SOC_SERVICES_H_
|
||||
#define __SOC_MARVELL_ARMADA38X_SOC_SERVICES_H_
|
||||
|
||||
#include <types.h>
|
||||
|
||||
extern u8 _memlayout_cbmem_top[];
|
||||
|
||||
#endif /*__SOC_MARVELL_ARMADA38X_SOC_SERVICES_H_*/
|
|
@ -0,0 +1,58 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2015 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/io.h>
|
||||
#include <timer.h>
|
||||
#include <delay.h>
|
||||
|
||||
#define TIMER_CTRL_REG 0xf1020300
|
||||
#define TIMER_RELOAD_REG 0xf1020310
|
||||
#define TIMER_REG 0xf1020314
|
||||
#define TIMER_RELOAD_VALUE 0xffffffff
|
||||
|
||||
#define MHZ_NUM 25
|
||||
|
||||
void init_timer(void)
|
||||
{
|
||||
unsigned int reg;
|
||||
|
||||
/* Set the reload timer */
|
||||
write32((void *)TIMER_RELOAD_REG, TIMER_RELOAD_VALUE);
|
||||
/* Set the initial value to TIMER_RELOAD_VALUE - 1
|
||||
* (instead of TIMER_RELOAD_VALUE) to avoid 'fake'
|
||||
* overflow being detected in timer_monotonic_get
|
||||
* if it's called close enough with 'this' function */
|
||||
write32((void *)TIMER_REG, TIMER_RELOAD_VALUE - 1);
|
||||
reg = read32((const void *)TIMER_CTRL_REG);
|
||||
/* Let it start counting */
|
||||
reg |= 0x3;
|
||||
write32((void *)TIMER_CTRL_REG, reg);
|
||||
}
|
||||
|
||||
void timer_monotonic_get(struct mono_time *mt)
|
||||
{
|
||||
static uint64_t total_ticks = 0;
|
||||
uint64_t overflow = 0;
|
||||
uint32_t current_ticks =
|
||||
TIMER_RELOAD_VALUE - read32((const void *)TIMER_REG);
|
||||
|
||||
/* Assuming at most one overflow happened since last call */
|
||||
if (current_ticks <= total_ticks)
|
||||
overflow = 1ULL << 32;
|
||||
|
||||
total_ticks = (((total_ticks + overflow) >> 32) << 32) + current_ticks;
|
||||
mono_time_set_usecs(mt, total_ticks / MHZ_NUM);
|
||||
}
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2015 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/io.h>
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <vendorcode/google/chromeos/chromeos.h>
|
||||
#include <symbols.h>
|
||||
|
||||
#define RESERVED_SIZE_KB (1 * KiB)
|
||||
|
||||
static void soc_enable(device_t dev)
|
||||
{
|
||||
/* Reserve bottom 1M bytes for MMU/TTB */
|
||||
reserved_ram_resource(dev, 0, ((uintptr_t)_dram / KiB +
|
||||
(CONFIG_DRAM_SIZE_MB * KiB - RESERVED_SIZE_KB)),
|
||||
RESERVED_SIZE_KB);
|
||||
ram_resource(dev, 0, (uintptr_t)_dram / KiB,
|
||||
(CONFIG_DRAM_SIZE_MB * KiB) - RESERVED_SIZE_KB);
|
||||
}
|
||||
|
||||
static void soc_init(device_t dev)
|
||||
{
|
||||
printk(BIOS_INFO, "CPU: Armada 38X\n");
|
||||
}
|
||||
|
||||
static struct device_operations soc_ops = {
|
||||
.read_resources = DEVICE_NOOP,
|
||||
.set_resources = DEVICE_NOOP,
|
||||
.enable_resources = soc_enable,
|
||||
.init = soc_init,
|
||||
.scan_bus = 0,
|
||||
};
|
||||
|
||||
static void enable_armada38x_dev(device_t dev)
|
||||
{
|
||||
dev->ops = &soc_ops;
|
||||
}
|
||||
|
||||
struct chip_operations soc_marvell_armada38x_ops = {
|
||||
CHIP_NAME("SOC Marvell Armada 38x")
|
||||
.enable_dev = enable_armada38x_dev,
|
||||
};
|
|
@ -0,0 +1,151 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2015 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/io.h>
|
||||
#include <console/uart.h>
|
||||
#include <console/console.h>
|
||||
#include <drivers/uart/uart8250reg.h>
|
||||
#include <boot/coreboot_tables.h>
|
||||
#include <stdint.h>
|
||||
#include <assert.h>
|
||||
#include <soc/common.h>
|
||||
|
||||
struct armada38x_uart {
|
||||
union {
|
||||
uint32_t thr; // Transmit holding register.
|
||||
uint32_t rbr; // Receive buffer register.
|
||||
uint32_t dll; // Divisor latch lsb.
|
||||
};
|
||||
union {
|
||||
uint32_t ier; // Interrupt enable register.
|
||||
uint32_t dlm; // Divisor latch msb.
|
||||
};
|
||||
union {
|
||||
uint32_t iir; // Interrupt identification register.
|
||||
uint32_t fcr; // FIFO control register.
|
||||
};
|
||||
uint32_t lcr; // Line control register.
|
||||
uint32_t mcr; // Modem control register.
|
||||
uint32_t lsr; // Line status register.
|
||||
uint32_t msr; // Modem status register.
|
||||
} __attribute__ ((packed));
|
||||
|
||||
static void armada38x_uart_tx_flush(struct armada38x_uart *uart_ptr);
|
||||
static int armada38x_uart_tst_byte(struct armada38x_uart *uart_ptr);
|
||||
|
||||
static void armada38x_uart_init(struct armada38x_uart *uart_ptr)
|
||||
{
|
||||
const uint8_t line_config = UART8250_LCR_WLS_8;
|
||||
uint16_t divisor = (u16) uart_baudrate_divisor(default_baudrate(),
|
||||
uart_platform_refclk(), 16);
|
||||
|
||||
armada38x_uart_tx_flush(uart_ptr);
|
||||
// Disable interrupts.
|
||||
write8(&uart_ptr->ier, 0);
|
||||
// Enable access to divisor latches.
|
||||
write8(&uart_ptr->lcr, UART8250_LCR_DLAB);
|
||||
// Set the divisor.
|
||||
write8(&uart_ptr->dll, divisor & 0xff);
|
||||
write8(&uart_ptr->dlm, (divisor >> 8) & 0xff);
|
||||
// Hide divisor latches and program line config.
|
||||
write8(&uart_ptr->lcr, line_config);
|
||||
// Enable FIFOs, and clear receive and transmit.
|
||||
write8(&uart_ptr->fcr, UART8250_FCR_FIFO_EN | UART8250_FCR_CLEAR_RCVR |
|
||||
UART8250_FCR_CLEAR_XMIT);
|
||||
}
|
||||
|
||||
static void armada38x_uart_tx_byte(struct armada38x_uart *uart_ptr,
|
||||
unsigned char data)
|
||||
{
|
||||
while (!(read8(&uart_ptr->lsr) & UART8250_LSR_THRE))
|
||||
;
|
||||
write8(&uart_ptr->thr, data);
|
||||
}
|
||||
|
||||
static void armada38x_uart_tx_flush(struct armada38x_uart *uart_ptr)
|
||||
{
|
||||
while (!(read8(&uart_ptr->lsr) & UART8250_LSR_TEMT))
|
||||
;
|
||||
}
|
||||
|
||||
static unsigned char armada38x_uart_rx_byte(struct armada38x_uart *uart_ptr)
|
||||
{
|
||||
if (!armada38x_uart_tst_byte(uart_ptr))
|
||||
return 0;
|
||||
return read8(&uart_ptr->rbr);
|
||||
}
|
||||
|
||||
static int armada38x_uart_tst_byte(struct armada38x_uart *uart_ptr)
|
||||
{
|
||||
return (read8(&uart_ptr->lsr) & UART8250_LSR_DR) == UART8250_LSR_DR;
|
||||
}
|
||||
|
||||
unsigned int uart_platform_refclk(void)
|
||||
{
|
||||
return MV_BOARD_TCLK_250MHZ;
|
||||
}
|
||||
|
||||
uintptr_t uart_platform_base(int idx)
|
||||
{
|
||||
/* Default to UART 0 */
|
||||
unsigned int base = CONFIG_CONSOLE_SERIAL_UART_ADDRESS;
|
||||
|
||||
assert((idx >= 0) && (idx < 2));
|
||||
base += idx * 0x100;
|
||||
return base;
|
||||
}
|
||||
|
||||
void uart_init(int idx)
|
||||
{
|
||||
struct armada38x_uart *uart_ptr = uart_platform_baseptr(idx);
|
||||
|
||||
armada38x_uart_init(uart_ptr);
|
||||
}
|
||||
|
||||
void uart_tx_byte(int idx, unsigned char data)
|
||||
{
|
||||
struct armada38x_uart *uart_ptr = uart_platform_baseptr(idx);
|
||||
|
||||
armada38x_uart_tx_byte(uart_ptr, data);
|
||||
}
|
||||
|
||||
void uart_tx_flush(int idx)
|
||||
{
|
||||
struct armada38x_uart *uart_ptr = uart_platform_baseptr(idx);
|
||||
|
||||
armada38x_uart_tx_flush(uart_ptr);
|
||||
}
|
||||
|
||||
unsigned char uart_rx_byte(int idx)
|
||||
{
|
||||
struct armada38x_uart *uart_ptr = uart_platform_baseptr(idx);
|
||||
|
||||
return armada38x_uart_rx_byte(uart_ptr);
|
||||
}
|
||||
|
||||
#if ENV_RAMSTAGE
|
||||
void uart_fill_lb(void *data)
|
||||
{
|
||||
struct lb_serial serial;
|
||||
|
||||
serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
|
||||
serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
|
||||
serial.baud = default_baudrate();
|
||||
serial.regwidth = 1;
|
||||
lb_add_serial(&serial, data);
|
||||
|
||||
lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
|
||||
}
|
||||
#endif
|
Loading…
Reference in New Issue