diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index 46721b0b84..a732fe6e8a 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -20,6 +20,25 @@
 #include <soc/vr_config.h>
 #include <stdint.h>
 
+/* Define config parameters for In-Band ECC (IBECC). */
+#define MAX_IBECC_REGIONS	8
+
+/* In-Band ECC Operation Mode */
+enum ibecc_mode {
+	IBECC_MODE_PER_REGION,
+	IBECC_MODE_NONE,
+	IBECC_MODE_ALL
+};
+
+struct ibecc_config {
+	bool enable;
+	enum ibecc_mode mode;
+	bool range_enable[MAX_IBECC_REGIONS];
+	uint16_t range_base[MAX_IBECC_REGIONS];
+	uint16_t range_mask[MAX_IBECC_REGIONS];
+	/* add ECC error injection if needed by a mainboard */
+};
+
 /* Types of different SKUs */
 enum soc_intel_alderlake_power_limits {
 	ADL_P_142_242_282_15W_CORE,
@@ -273,6 +292,9 @@ struct soc_intel_alderlake_config {
 	/* TCC activation offset */
 	uint32_t tcc_offset;
 
+	/* In-Band ECC (IBECC) configuration */
+	struct ibecc_config ibecc;
+
 	/* System Agent dynamic frequency support. Only effects ULX/ULT CPUs.
 	 * When enabled memory will be training at two different frequencies.
 	 * 0:Disabled, 1:FixedPoint0, 2:FixedPoint1, 3:FixedPoint2,
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index c0bdb0de2b..b603a42f01 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -342,6 +342,24 @@ static void fill_fspm_trace_params(FSP_M_CONFIG *m_cfg,
 	m_cfg->CpuCrashLogEnable = m_cfg->CpuCrashLogDevice;
 }
 
+static void fill_fspm_ibecc_params(FSP_M_CONFIG *m_cfg,
+		const struct soc_intel_alderlake_config *config)
+{
+	/* In-Band ECC configuration */
+	if (config->ibecc.enable) {
+		m_cfg->Ibecc = config->ibecc.enable;
+		m_cfg->IbeccOperationMode = config->ibecc.mode;
+		if (m_cfg->IbeccOperationMode == IBECC_MODE_PER_REGION) {
+			FSP_ARRAY_LOAD(m_cfg->IbeccProtectedRangeEnable,
+				       config->ibecc.range_enable);
+			FSP_ARRAY_LOAD(m_cfg->IbeccProtectedRangeBase,
+				       config->ibecc.range_base);
+			FSP_ARRAY_LOAD(m_cfg->IbeccProtectedRangeMask,
+				       config->ibecc.range_mask);
+		}
+	}
+}
+
 static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
 		const struct soc_intel_alderlake_config *config)
 {
@@ -362,6 +380,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
 		fill_fspm_usb4_params,
 		fill_fspm_vtd_params,
 		fill_fspm_trace_params,
+		fill_fspm_ibecc_params,
 	};
 
 	for (size_t i = 0; i < ARRAY_SIZE(fill_fspm_params); i++)