soc/amd/stoneyridge: Remove UDELAY_LAPIC_FIXED_FSB

We only need this defined with udelay() implementation
on top of LAPIC_MONOTONIC_TIMER.

Change-Id: I490245fa0d57de3a6e8609e735f668626cf1201e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36526
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2019-10-31 15:47:03 +02:00
parent 432516586e
commit 2ca11a527c
1 changed files with 0 additions and 4 deletions

View File

@ -86,10 +86,6 @@ config VBOOT
select VBOOT_VBNV_CMOS
select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
config UDELAY_LAPIC_FIXED_FSB
int
default 200
# TODO: Sync these with definitions in PI vendorcode.
# DCACHE_RAM_BASE must equal BSP_STACK_BASE_ADDR.
# DCACHE_RAM_SIZE must equal BSP_STACK_SIZE.