Add AMD C32 support.
It is based on other existing Fam10 code. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6464 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Zheng Bao
Zheng Bao
parent
c3422235b1
commit
2ca2f17724
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@ -8,6 +8,7 @@ source src/cpu/amd/socket_940/Kconfig
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source src/cpu/amd/socket_AM2/Kconfig
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source src/cpu/amd/socket_AM2r2/Kconfig
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source src/cpu/amd/socket_AM3/Kconfig
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source src/cpu/amd/socket_C32/Kconfig
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source src/cpu/amd/socket_ASB2/Kconfig
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source src/cpu/amd/socket_F/Kconfig
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source src/cpu/amd/socket_F_1207/Kconfig
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@ -7,6 +7,7 @@ subdirs-$(CONFIG_CPU_AMD_SOCKET_AM2) += socket_AM2
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subdirs-$(CONFIG_CPU_AMD_SOCKET_AM2R2) += socket_AM2r2
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subdirs-$(CONFIG_CPU_AMD_SOCKET_AM3) += socket_AM3
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subdirs-$(CONFIG_CPU_AMD_SOCKET_ASB2) += socket_ASB2
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subdirs-$(CONFIG_CPU_AMD_SOCKET_C32) += socket_C32
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subdirs-$(CONFIG_CPU_AMD_GX1) += model_gx1
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subdirs-$(CONFIG_CPU_AMD_GX2) += model_gx2
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subdirs-$(CONFIG_CPU_AMD_LX) += model_lx
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@ -89,9 +89,25 @@ static const struct {
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0x00000000, 1 << (33-32),
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0x00000000, 1 << (33-32) }, /* [ExtendedFeatEn]=1 */
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{ BU_CFG2, AMD_DRBH_Cx , AMD_PTYPE_ALL,
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{ BU_CFG2, AMD_DRBH_Cx, AMD_PTYPE_ALL,
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0x00000000, 1 << (35-32),
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0x00000000, 1 << (35-32) }, /* Erratum 343 (set to 0 after CAR, in post_cache_as_ram()/model_10xxx_init() ) */
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{ OSVW_ID_Length, AMD_DR_Bx | AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL,
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0x00000004, 0x00000000,
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0x00000004, 0x00000000}, /* B0 or Above, OSVW_ID_Length is 0004h */
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{ OSVW_Status, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_MC,
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0x0000000C, 0x00000000,
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0x0000000C, 0x00000000}, /* Cx and Dx multiple-link processor */
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{ BU_CFG2, AMD_DR_Dx, AMD_PTYPE_ALL,
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0x00000000, 1 << (50-32),
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0x00000000, 1 << (50-32)}, /* D0 or Above, RdMmExtCfgQwEn*/
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{ CPU_ID_EXT_FEATURES_MSR, AMD_DR_Dx, AMD_PTYPE_ALL,
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0x00000000, 1 << (51 - 32),
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0x00000000, 1 << (51 - 32)}, /* G34_PKG | C32_PKG | S1G4_PKG | ASB2_PKG */
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};
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@ -140,28 +156,28 @@ static const struct {
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* program Link Global Extended Control Register[ForceFullT0]
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* (F0x16C[15:13]) to 000b */
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{ 0, 0x170, AMD_DRBA23_RBC2, AMD_PTYPE_ALL, /* FIXME Should include BL_C2 but there is no constant */
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{ 0, 0x170, AMD_FAM10_ALL, AMD_PTYPE_ALL, /* Fix FAM10_ALL when fixed in rev guide */
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0x00000000, 0x00000100 },
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{ 0, 0x174, AMD_DRBA23_RBC2, AMD_PTYPE_ALL,
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{ 0, 0x174, AMD_FAM10_ALL, AMD_PTYPE_ALL,
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0x00000000, 0x00000100 },
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{ 0, 0x178, AMD_DRBA23_RBC2, AMD_PTYPE_ALL,
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{ 0, 0x178, AMD_FAM10_ALL, AMD_PTYPE_ALL,
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0x00000000, 0x00000100 },
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{ 0, 0x17C, AMD_DRBA23_RBC2, AMD_PTYPE_ALL,
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{ 0, 0x17C, AMD_FAM10_ALL, AMD_PTYPE_ALL,
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0x00000000, 0x00000100 },
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{ 0, 0x180, AMD_DRBA23_RBC2, AMD_PTYPE_ALL,
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{ 0, 0x180, AMD_FAM10_ALL, AMD_PTYPE_ALL,
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0x00000000, 0x00000100 },
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{ 0, 0x184, AMD_DRBA23_RBC2, AMD_PTYPE_ALL,
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{ 0, 0x184, AMD_FAM10_ALL, AMD_PTYPE_ALL,
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0x00000000, 0x00000100 },
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{ 0, 0x188, AMD_DRBA23_RBC2, AMD_PTYPE_ALL,
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{ 0, 0x188, AMD_FAM10_ALL, AMD_PTYPE_ALL,
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0x00000000, 0x00000100 },
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{ 0, 0x18C, AMD_DRBA23_RBC2, AMD_PTYPE_ALL,
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{ 0, 0x18C, AMD_FAM10_ALL, AMD_PTYPE_ALL,
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0x00000000, 0x00000100 },
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{ 0, 0x170, AMD_DRBA23_RBC2, AMD_PTYPE_ALL,
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{ 0, 0x170, AMD_FAM10_ALL, AMD_PTYPE_ALL,
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0x00000000, 0x00000100 },
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/* Link Global Extended Control Register */
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{ 0, 0x16C, AMD_DRBA23_RBC2, AMD_PTYPE_ALL,
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0x00000014, 0x0000E03F }, /* [15:13] ForceFullT0 = 0b,
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{ 0, 0x16C, AMD_FAM10_ALL, AMD_PTYPE_ALL,
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0x00000014, 0x0000003F }, /* [15:13] ForceFullT0 = 0b,
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* Set T0Time 14h per BKDG */
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@ -297,7 +313,7 @@ static const struct {
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[5] DisPciCfgCpuMstAbtRsp = 1,
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[1] SyncFloodOnUsPwDataErr = 1 */
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/* errata 346 - Fam10 C2 -- FIXME at 25.6.2010 should apply to BL-C[23] too but I can't find their constants
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/* errata 346 - Fam10 C2, C3
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* System software should set F3x188[22] to 1b. */
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{ 3, 0x188, AMD_DR_Cx, AMD_PTYPE_ALL,
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0x00400000, 0x00400000 },
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@ -324,100 +340,100 @@ static const struct {
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u32 mask;
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} fam10_htphy_default[] = {
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/* Errata 344 - Fam10 C2/D0 -- FIXME at 25.6.2010 should be for ((RB|BL|DA)-C[23])|(HY-D[01])|(PH-E0) but I don't find constants for all of them
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/* Errata 344 - Fam10 C2/C3, D0/D1
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* System software should set bit 6 of F4x1[9C, 94, 8C, 84]_x[78:70, 68:60]. */
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{ 0x60, AMD_DRBH_Cx , AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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{ 0x60, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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0x00000040, 0x00000040 },
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{ 0x61, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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{ 0x61, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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0x00000040, 0x00000040 },
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{ 0x62, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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{ 0x62, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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0x00000040, 0x00000040 },
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{ 0x63, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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{ 0x63, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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0x00000040, 0x00000040 },
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{ 0x64, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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{ 0x64, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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0x00000040, 0x00000040 },
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{ 0x65, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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{ 0x65, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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0x00000040, 0x00000040 },
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{ 0x66, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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{ 0x66, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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0x00000040, 0x00000040 },
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{ 0x67, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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{ 0x67, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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0x00000040, 0x00000040 },
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{ 0x68, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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{ 0x68, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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0x00000040, 0x00000040 },
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{ 0x70, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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{ 0x70, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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0x00000040, 0x00000040 },
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{ 0x71, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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{ 0x71, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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0x00000040, 0x00000040 },
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{ 0x72, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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{ 0x72, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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0x00000040, 0x00000040 },
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{ 0x73, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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{ 0x73, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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0x00000040, 0x00000040 },
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{ 0x74, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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{ 0x74, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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0x00000040, 0x00000040 },
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{ 0x75, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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{ 0x75, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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0x00000040, 0x00000040 },
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{ 0x76, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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{ 0x76, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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0x00000040, 0x00000040 },
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{ 0x77, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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{ 0x77, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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0x00000040, 0x00000040 },
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{ 0x78, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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{ 0x78, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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0x00000040, 0x00000040 },
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/* Errata 354 - Fam10 C2 - FIXME at 25.6.2010 affects RB-C2, BL-C2,DA-C2,RB-C3,BL-C3,DA-C3, but BL-C[23] have no constants
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/* Errata 354 - Fam10 C2, C3
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* System software should set bit 6 of F4x1[9C,94,8C,84]_x[58:50, 48:40] for all links. */
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{ 0x40, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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{ 0x40, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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0x00000040, 0x00000040 },
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{ 0x41, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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{ 0x41, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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0x00000040, 0x00000040 },
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{ 0x42, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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{ 0x42, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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0x00000040, 0x00000040 },
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{ 0x43, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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{ 0x43, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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0x00000040, 0x00000040 },
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{ 0x44, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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{ 0x44, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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0x00000040, 0x00000040 },
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{ 0x45, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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{ 0x45, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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0x00000040, 0x00000040 },
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{ 0x46, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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{ 0x46, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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0x00000040, 0x00000040 },
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{ 0x47, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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{ 0x47, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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0x00000040, 0x00000040 },
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{ 0x48, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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{ 0x48, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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0x00000040, 0x00000040 },
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{ 0x50, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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{ 0x50, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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0x00000040, 0x00000040 },
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{ 0x51, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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{ 0x51, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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0x00000040, 0x00000040 },
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{ 0x52, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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{ 0x52, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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0x00000040, 0x00000040 },
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{ 0x53, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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{ 0x53, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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0x00000040, 0x00000040 },
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{ 0x54, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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{ 0x54, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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0x00000040, 0x00000040 },
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{ 0x55, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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{ 0x55, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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0x00000040, 0x00000040 },
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{ 0x56, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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{ 0x56, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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0x00000040, 0x00000040 },
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{ 0x57, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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{ 0x57, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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0x00000040, 0x00000040 },
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{ 0x58, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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{ 0x58, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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0x00000040, 0x00000040 },
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/* Errata 327 - Fam10 C2/D0
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/* Errata 327 - Fam10 C2/C3, D0/D1
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* BIOS should set the Link Phy Impedance Register[RttCtl]
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* (F4x1[9C, 94, 8C, 84]_x[D0, C0][31:29]) to 010b and
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* Link Phy Impedance Register[RttIndex]
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* (F4x1[9C, 94, 8C, 84]_x[D0, C0][20:16]) to 00100b */
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{ 0xC0, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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{ 0xC0, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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0x40040000, 0xe01F0000 },
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{ 0xD0, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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{ 0xD0, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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0x40040000, 0xe01F0000 },
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{ 0x520A, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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{ 0x520A,AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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0x00004000, 0x00006000 }, /* HT_PHY_DLL_REG */
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{ 0x530A, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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{ 0x530A, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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0x00004000, 0x00006000 }, /* HT_PHY_DLL_REG */
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{ 0x520A, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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@ -0,0 +1,186 @@
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/*
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******************************************************************************
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*
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* Copyright 2010 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
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*
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||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
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* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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||||
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||||
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||||
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|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
|
@ -145,6 +145,7 @@ static struct cpu_device_id cpu_table[] = {
|
|||
{ X86_VENDOR_AMD, 0x100F62 }, /* DA-C2 */
|
||||
{ X86_VENDOR_AMD, 0x100F63 }, /* DA-C3 */
|
||||
{ X86_VENDOR_AMD, 0x100F80 }, /* HY-D0 */
|
||||
{ X86_VENDOR_AMD, 0x100F81 }, /* HY-D1 */
|
||||
{ 0, 0 },
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -154,6 +154,25 @@ static const struct str_s String2_socket_AM2[] = {
|
|||
{0, 0, 0, NULL}
|
||||
};
|
||||
|
||||
static const struct str_s String1_socket_C32[] = {
|
||||
{0x00, 0x03, 0x00, "AMD Opteron(tm) Processor 41"},
|
||||
{0x00, 0x05, 0x00, "AMD Opteron(tm) Processor 41"},
|
||||
{0x01, 0x03, 0x01, "Embedded AMD Opteron(tm) Processor "},
|
||||
{0x01, 0x05, 0x01, "Embedded AMD Opteron(tm) Processor "},
|
||||
{0, 0, 0, NULL}
|
||||
};
|
||||
|
||||
static const struct str_s String2_socket_C32[] = {
|
||||
{0x00, 0x03, 0x00, " HE"},
|
||||
{0x00, 0x03, 0x01, " EE"},
|
||||
{0x00, 0x05, 0x00, " HE"},
|
||||
{0x00, 0x05, 0x01, " EE"},
|
||||
{0x01, 0x03, 0x01, "QS HE"},
|
||||
{0x01, 0x03, 0x02, "LE HE"},
|
||||
{0x01, 0x05, 0x01, "KX HE"},
|
||||
{0x01, 0x05, 0x02, "GL EE"},
|
||||
{0, 0, 0, NULL}
|
||||
};
|
||||
|
||||
const char const *unknown = "AMD Processor model unknown";
|
||||
const char const *unknown2 = " type unknown";
|
||||
|
|
@ -218,6 +237,10 @@ int init_processor_name(void)
|
|||
str = String1_socket_AM2;
|
||||
str2 = String2_socket_AM2;
|
||||
break;
|
||||
case 5: /* C32 */
|
||||
str = String1_socket_C32;
|
||||
str2 = String2_socket_C32;
|
||||
break;
|
||||
default:
|
||||
goto done;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -50,6 +50,7 @@ static const u8 microcode_updates[] __attribute__ ((aligned(16))) = {
|
|||
* 00100F43h (RB-C3) 1043h 010000b6h
|
||||
* 00100F62h (DA-C2) 1062h 0100009Fh
|
||||
* 00100F63h (DA-C3) 1043h 010000b6h
|
||||
* 00100F81h (HY-D1) 1081h 010000c4h
|
||||
*/
|
||||
|
||||
#include CONFIG_AMD_UCODE_PATCH_FILE
|
||||
|
|
@ -76,6 +77,7 @@ static u32 get_equivalent_processor_rev_id(u32 orig_id) {
|
|||
0x100f43, 0x1043,
|
||||
0x100f62, 0x1062,
|
||||
0x100f63, 0x1043,
|
||||
0x100f81, 0x1081,
|
||||
};
|
||||
|
||||
u32 new_id;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,42 @@
|
|||
config CPU_AMD_SOCKET_C32
|
||||
bool
|
||||
select CPU_AMD_MODEL_10XXX
|
||||
select HT3_SUPPORT
|
||||
select PCI_IO_CFG_EXT
|
||||
select CACHE_AS_RAM
|
||||
|
||||
config CPU_SOCKET_TYPE
|
||||
hex
|
||||
default 0x14
|
||||
depends on CPU_AMD_SOCKET_C32
|
||||
|
||||
config EXT_RT_TBL_SUPPORT
|
||||
bool
|
||||
default n
|
||||
depends on CPU_AMD_SOCKET_C32
|
||||
|
||||
config EXT_CONF_SUPPORT
|
||||
bool
|
||||
default n
|
||||
depends on CPU_AMD_SOCKET_C32
|
||||
|
||||
config CBB
|
||||
hex
|
||||
default 0x0
|
||||
depends on CPU_AMD_SOCKET_C32
|
||||
|
||||
config CDB
|
||||
hex
|
||||
default 0x18
|
||||
depends on CPU_AMD_SOCKET_C32
|
||||
|
||||
config XIP_ROM_BASE
|
||||
hex
|
||||
default 0xfff80000
|
||||
depends on CPU_AMD_SOCKET_C32
|
||||
|
||||
config XIP_ROM_SIZE
|
||||
hex
|
||||
default 0x80000
|
||||
depends on CPU_AMD_SOCKET_C32
|
||||
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
ramstage-y += socket_C32.c
|
||||
subdirs-y += ../model_10xxx
|
||||
subdirs-y += ../quadcore
|
||||
subdirs-y += ../mtrr
|
||||
subdirs-y += ../microcode
|
||||
subdirs-y += ../../x86/tsc
|
||||
subdirs-y += ../../x86/lapic
|
||||
subdirs-y += ../../x86/cache
|
||||
subdirs-y += ../../x86/pae
|
||||
subdirs-y += ../../x86/mtrr
|
||||
subdirs-y += ../../x86/smm
|
||||
subdirs-y += ../smm
|
||||
|
||||
cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
extern struct chip_operations cpu_amd_socket_C32_ops;
|
||||
|
||||
struct cpu_amd_socket_C32_config {
|
||||
};
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <device/device.h>
|
||||
#include "chip.h"
|
||||
|
||||
struct chip_operations cpu_amd_socket_C32_ops = {
|
||||
CHIP_NAME("socket C32")
|
||||
};
|
||||
|
|
@ -78,6 +78,9 @@ static void print_t(const char *strval)
|
|||
#elif CONFIG_CPU_SOCKET_TYPE == 0x13
|
||||
//ASB2
|
||||
#include "../amdmct/mct_ddr3/mctardk5.c"
|
||||
//C32
|
||||
#elif CONFIG_CPU_SOCKET_TYPE == 0x14
|
||||
#include "../amdmct/mct_ddr3/mctardk5.c"
|
||||
#endif
|
||||
|
||||
#else /* DDR2 */
|
||||
|
|
@ -205,6 +208,9 @@ u32 mctGetLogicalCPUID(u32 Node)
|
|||
case 0x10080:
|
||||
ret = AMD_HY_D0;
|
||||
break;
|
||||
case 0x10081:
|
||||
ret = AMD_HY_D1;
|
||||
break;
|
||||
default:
|
||||
/* FIXME: mabe we should die() here. */
|
||||
print_err("FIXME! CPU Version unknown or not supported! \n");
|
||||
|
|
|
|||
|
|
@ -45,6 +45,7 @@
|
|||
#define AMD_HY_D0 0x04000000 /* Istanbul D0 */
|
||||
#define AMD_RB_C3 0x08000000 /* ??? C3 */
|
||||
#define AMD_DA_C3 0x10000000 /* XXXX C3 */
|
||||
#define AMD_HY_D1 0x20000000 /* Istanbul D1 */
|
||||
|
||||
/*
|
||||
* Groups - Create as many as you wish, from the above public values
|
||||
|
|
@ -61,19 +62,18 @@
|
|||
#define AMD_DR_LT_B2 (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_BA)
|
||||
#define AMD_DR_LT_B3 (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_B2 | AMD_DR_BA)
|
||||
#define AMD_DR_GT_B0 (AMD_DR_ALL & ~(AMD_DR_B0))
|
||||
#define AMD_DR_GT_Bx (AMD_DR_ALL & ~(AMD_DR_Ax | AMD_DR_Bx))
|
||||
#define AMD_DR_ALL (AMD_DR_Bx)
|
||||
#define AMD_FAM10_ALL (AMD_DR_ALL | AMD_RB_C2 | AMD_HY_D0 | AMD_DA_C3 | AMD_DA_C2 | AMD_RB_C3 )
|
||||
#define AMD_FAM10_ALL (AMD_DR_ALL | AMD_RB_C2 | AMD_HY_D0 | AMD_DA_C3 | AMD_DA_C2 | AMD_RB_C3 | AMD_HY_D1)
|
||||
#define AMD_FAM10_LT_D (AMD_FAM10_ALL & ~(AMD_HY_D0))
|
||||
#define AMD_FAM10_GT_B0 (AMD_FAM10_ALL & ~(AMD_DR_B0))
|
||||
#define AMD_DA_Cx (AMD_DA_C2 | AMD_DA_C3)
|
||||
#define AMD_DR_Cx (AMD_RB_C2 | AMD_RB_C3 | AMD_DA_Cx)
|
||||
#define AMD_FAM10_C3 (AMD_RB_C3 | AMD_DA_C3)
|
||||
#define AMD_DR_Dx (AMD_HY_D0)
|
||||
#define AMD_DRBH_Cx (AMD_DR_Cx | AMD_HY_D0 )
|
||||
#define AMD_DRBA23_RBC2 (AMD_DR_BA | AMD_DR_B2 | AMD_DR_B3 | AMD_RB_C2 )
|
||||
|
||||
#define AMD_DR_GT_Bx (AMD_DR_ALL & ~(AMD_DR_Ax | AMD_DR_Bx))
|
||||
#define AMD_DR_DAC2_OR_C3 (AMD_DA_C2 | AMD_DA_C3)
|
||||
#define AMD_DR_Dx (AMD_HY_D0 | AMD_HY_D1)
|
||||
#define AMD_DRBH_Cx (AMD_DR_Cx | AMD_HY_D0 )
|
||||
#define AMD_DRBA23_RBC2 (AMD_DR_BA | AMD_DR_B2 | AMD_DR_B3 | AMD_RB_C2 )
|
||||
#define AMD_DR_DAC2_OR_C3 (AMD_DA_C2 | AMD_DA_C3 | AMD_RB_C3)
|
||||
|
||||
/*
|
||||
* Public Platforms - USE THESE VERSIONS TO MAKE COMPARE WITH CPUPLATFORMTYPE RETURN VALUE
|
||||
|
|
|
|||
|
|
@ -2407,7 +2407,7 @@ static void mct_DramInit(struct MCTStatStruc *pMCTstat,
|
|||
// FIXME: for rev A: mct_BeforeDramInit_D(pDCTstat, dct);
|
||||
|
||||
/* Disable auto refresh before Dram init when in ganged mode (Erratum 278) */
|
||||
if (pDCTstat->LogicalCPUID & AMD_DR_LT_B2) {
|
||||
if (pDCTstat->LogicalCPUID & (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_BA)) {
|
||||
if (pDCTstat->GangedMode) {
|
||||
val = Get_NB32(pDCTstat->dev_dct, 0x8C + (0x100 * dct));
|
||||
val |= 1 << DisAutoRefresh;
|
||||
|
|
@ -2421,7 +2421,7 @@ static void mct_DramInit(struct MCTStatStruc *pMCTstat,
|
|||
* to ensure both DCTs are in sync (Erratum 278)
|
||||
*/
|
||||
|
||||
if (pDCTstat->LogicalCPUID & AMD_DR_LT_B2) {
|
||||
if (pDCTstat->LogicalCPUID & (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_BA)) {
|
||||
if (pDCTstat->GangedMode) {
|
||||
do {
|
||||
val = Get_NB32(pDCTstat->dev_dct, 0x90 + (0x100 * dct));
|
||||
|
|
|
|||
Loading…
Reference in New Issue