GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/google/sarien: Create VR config settings 

Create VR settings configuration as per board design.

BUG=N/A
TEST=Build and boot up into sarien platform.

Change-Id: Ic196fd80e5211bd5146158d4d340b52c850a4e62
Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com>
Reviewed-on: https://review.coreboot.org/c/31404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
Roy Mingi Park 2019-02-13 11:03:23 -08:00 committed by Patrick Georgi
parent 23e3013830
commit 2cb7de09b2
2 changed files with 152 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

76
src/mainboard/google/sarien/variants/arcada/devicetree.cb
View File

@ -42,6 +42,82 @@ chip soc/intel/cannonlake
register "SlowSlewRateForSa" = "0" register "SlowSlewRateForSa" = "0"
register "SlowSlewRateForFivr" = "0" register "SlowSlewRateForFivr" = "0"
# VR Settings Configuration for 4 Domains
#+----------------+-------+-------+-------+-------+
#| Domain/Setting | SA | IA | GTUS | GTS |
#+----------------+-------+-------+-------+-------+
#| Psi1Threshold | 20A | 20A | 20A | 20A |
#| Psi2Threshold | 5A | 5A | 5A | 5A |
#| Psi3Threshold | 1A | 1A | 1A | 1A |
#| Psi3Enable | 1 | 1 | 1 | 1 |
#| Psi4Enable | 1 | 1 | 1 | 1 |
#| ImonSlope | 0 | 0 | 0 | 0 |
#| ImonOffset | 0 | 0 | 0 | 0 |
#| IccMax | 6A | 70A | 31A | 31A |
#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
#| AcLoadline | 10.3 | 1.8 | 3.1 | 3.1 |
#| DcLoadline | 10.3 | 1.8 | 3.1 | 3.1 |
#+----------------+-------+-------+-------+-------+
register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
.vr_config_enable = 1,
.psi1threshold = VR_CFG_AMP(20),
.psi2threshold = VR_CFG_AMP(5),
.psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1,
.psi4enable = 1,
.imon_slope = 0x0,
.imon_offset = 0x0,
.icc_max = VR_CFG_AMP(6),
.voltage_limit = 1520,
.ac_loadline = 1030,
.dc_loadline = 1030,
}"
register "domain_vr_config[VR_IA_CORE]" = "{
.vr_config_enable = 1,
.psi1threshold = VR_CFG_AMP(20),
.psi2threshold = VR_CFG_AMP(5),
.psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1,
.psi4enable = 1,
.imon_slope = 0x0,
.imon_offset = 0x0,
.icc_max = VR_CFG_AMP(70),
.voltage_limit = 1520,
.ac_loadline = 180,
.dc_loadline = 180,
}"
register "domain_vr_config[VR_GT_UNSLICED]" = "{
.vr_config_enable = 1,
.psi1threshold = VR_CFG_AMP(20),
.psi2threshold = VR_CFG_AMP(5),
.psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1,
.psi4enable = 1,
.imon_slope = 0x0,
.imon_offset = 0x0,
.icc_max = VR_CFG_AMP(31),
.voltage_limit = 1520,
.ac_loadline = 310,
.dc_loadline = 310,
}"
register "domain_vr_config[VR_GT_SLICED]" = "{
.vr_config_enable = 1,
.psi1threshold = VR_CFG_AMP(20),
.psi2threshold = VR_CFG_AMP(5),
.psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1,
.psi4enable = 1,
.imon_slope = 0x0,
.imon_offset = 0x0,
.icc_max = VR_CFG_AMP(31),
.voltage_limit = 1520,
.ac_loadline = 310,
.dc_loadline = 310,
}"
# Intel Common SoC Config # Intel Common SoC Config
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port
register "usb2_ports[1]" = "USB2_PORT_LONG(OC0)" # Left Type-A Port register "usb2_ports[1]" = "USB2_PORT_LONG(OC0)" # Left Type-A Port

76
src/mainboard/google/sarien/variants/sarien/devicetree.cb
View File

@ -46,6 +46,82 @@ chip soc/intel/cannonlake
register "tdp_pl2_override" = "51" register "tdp_pl2_override" = "51"
register "Device4Enable" = "1" register "Device4Enable" = "1"
# VR Settings Configuration for 4 Domains
#+----------------+-------+-------+-------+-------+
#| Domain/Setting | SA | IA | GTUS | GTS |
#+----------------+-------+-------+-------+-------+
#| Psi1Threshold | 20A | 20A | 20A | 20A |
#| Psi2Threshold | 5A | 5A | 5A | 5A |
#| Psi3Threshold | 1A | 1A | 1A | 1A |
#| Psi3Enable | 1 | 1 | 1 | 1 |
#| Psi4Enable | 1 | 1 | 1 | 1 |
#| ImonSlope | 0 | 0 | 0 | 0 |
#| ImonOffset | 0 | 0 | 0 | 0 |
#| IccMax | 6A | 70A | 31A | 31A |
#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
#| AcLoadline | 10.3 | 1.8 | 3.1 | 3.1 |
#| DcLoadline | 10.3 | 1.8 | 3.1 | 3.1 |
#+----------------+-------+-------+-------+-------+
register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
.vr_config_enable = 1,
.psi1threshold = VR_CFG_AMP(20),
.psi2threshold = VR_CFG_AMP(5),
.psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1,
.psi4enable = 1,
.imon_slope = 0x0,
.imon_offset = 0x0,
.icc_max = VR_CFG_AMP(6),
.voltage_limit = 1520,
.ac_loadline = 1030,
.dc_loadline = 1030,
}"
register "domain_vr_config[VR_IA_CORE]" = "{
.vr_config_enable = 1,
.psi1threshold = VR_CFG_AMP(20),
.psi2threshold = VR_CFG_AMP(5),
.psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1,
.psi4enable = 1,
.imon_slope = 0x0,
.imon_offset = 0x0,
.icc_max = VR_CFG_AMP(70),
.voltage_limit = 1520,
.ac_loadline = 180,
.dc_loadline = 180,
}"
register "domain_vr_config[VR_GT_UNSLICED]" = "{
.vr_config_enable = 1,
.psi1threshold = VR_CFG_AMP(20),
.psi2threshold = VR_CFG_AMP(5),
.psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1,
.psi4enable = 1,
.imon_slope = 0x0,
.imon_offset = 0x0,
.icc_max = VR_CFG_AMP(31),
.voltage_limit = 1520,
.ac_loadline = 310,
.dc_loadline = 310,
}"
register "domain_vr_config[VR_GT_SLICED]" = "{
.vr_config_enable = 1,
.psi1threshold = VR_CFG_AMP(20),
.psi2threshold = VR_CFG_AMP(5),
.psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1,
.psi4enable = 1,
.imon_slope = 0x0,
.imon_offset = 0x0,
.icc_max = VR_CFG_AMP(31),
.voltage_limit = 1520,
.ac_loadline = 310,
.dc_loadline = 310,
}"
# Intel Common SoC Config # Intel Common SoC Config
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port
register "usb2_ports[1]" = "USB2_PORT_LONG(OC0)" # Right Type-A Port 1 register "usb2_ports[1]" = "USB2_PORT_LONG(OC0)" # Right Type-A Port 1