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Enable SPI cacheline prefetch early to reduce boot time. 

Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6584 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Scott Duplichan 2011-05-15 21:54:04 +00:00 committed by Marc Jones
parent d9a634c756
commit 2cc5f550c7
1 changed files with 7 additions and 0 deletions
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7
src/mainboard/amd/persimmon/romstage.c
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@ -50,6 +50,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
__writemsr (0xc0010062, 0); __writemsr (0xc0010062, 0);
// early enable of PrefetchEnSPIFromHost
if (boot_cpu())
{
__outdword (0xcf8, 0x8000a3b8);
__outdword (0xcfc, __indword (0xcfc) | 0 << 24);
}
// early enable of SPI 33 MHz fast mode read // early enable of SPI 33 MHz fast mode read
if (boot_cpu()) if (boot_cpu())
{ {