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nb/intel/sandybridge: Drop iommu.c and rename functions 

* Move the contents of iommu.c to early_init.c.
* Name the functions like done in intel/soc/common.
* Move PAMx register setup to own function

Preparations for integration in soc/intel/common/*

Tested on Lenovo T520 (Intel Sandy Bridge).
Still boots to OS, no errors visible in dmesg.

Change-Id: I3ec395bf6722bceb84316e92733dcfcd7a093639
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32068
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Patrick Rudolph 2019-03-24 18:08:43 +01:00 committed by Felix Held
parent 343e13489e
commit 2cdb65d663
5 changed files with 47 additions and 63 deletions
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1
src/northbridge/intel/sandybridge/Makefile.inc
View File

@ -43,7 +43,6 @@ mrc.bin-position := 0xfffa0000
mrc.bin-type := mrc
endif
romstage-y += romstage.c
romstage-y += iommu.c
romstage-y += early_init.c
romstage-y += ../../../arch/x86/walkcbfs.S

55
src/northbridge/intel/sandybridge/early_init.c
View File

@ -2,7 +2,9 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2010 coresystems GmbH
* Copyright (C) 2015 secunet Security Networks AG
* Copyright (C) 2011 Google Inc
* Copyright (C) 2018 Patrick Rudolph <patrick.rudolph@9elements.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -17,6 +19,8 @@
#include <stdlib.h>
#include <console/console.h>
#include <arch/io.h>
#include <device/mmio.h>
#include <device/device.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <pc80/mc146818rtc.h>
@ -25,6 +29,41 @@
#include "sandybridge.h"
static void systemagent_vtd_init(void)
{
const u32 capid0_a = pci_read_config32(PCI_DEV(0, 0, 0), CAPID0_A);
if (capid0_a & (1 << 23))
return;
/* setup BARs */
MCHBAR32(0x5404) = IOMMU_BASE1 >> 32;
MCHBAR32(0x5400) = IOMMU_BASE1 | 1;
MCHBAR32(0x5414) = IOMMU_BASE2 >> 32;
MCHBAR32(0x5410) = IOMMU_BASE2 | 1;
/* lock policies */
write32((void *)(IOMMU_BASE1 + 0xff0), 0x80000000);
const struct device *const azalia = pcidev_on_root(0x1b, 0);
if (azalia && azalia->enabled) {
write32((void *)(IOMMU_BASE2 + 0xff0), 0x20000000);
write32((void *)(IOMMU_BASE2 + 0xff0), 0xa0000000);
} else {
write32((void *)(IOMMU_BASE2 + 0xff0), 0x80000000);
}
}
static void enable_pam_region(void)
{
pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30);
pci_write_config8(PCI_DEV(0, 0x00, 0), PAM1, 0x33);
pci_write_config8(PCI_DEV(0, 0x00, 0), PAM2, 0x33);
pci_write_config8(PCI_DEV(0, 0x00, 0), PAM3, 0x33);
pci_write_config8(PCI_DEV(0, 0x00, 0), PAM4, 0x33);
pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33);
pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33);
}
static void sandybridge_setup_bars(void)
{
printk(BIOS_DEBUG, "Setting up static northbridge registers...");
@ -36,15 +75,6 @@ static void sandybridge_setup_bars(void)
pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1);
pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, (0LL+(uintptr_t)DEFAULT_DMIBAR) >> 32);
/* Set C0000-FFFFF to access RAM on both reads and writes */
pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30);
pci_write_config8(PCI_DEV(0, 0x00, 0), PAM1, 0x33);
pci_write_config8(PCI_DEV(0, 0x00, 0), PAM2, 0x33);
pci_write_config8(PCI_DEV(0, 0x00, 0), PAM3, 0x33);
pci_write_config8(PCI_DEV(0, 0x00, 0), PAM4, 0x33);
pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33);
pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33);
printk(BIOS_DEBUG, " done\n");
}
@ -156,7 +186,7 @@ static void start_peg_link_training(void)
}
}
void sandybridge_early_initialization(void)
void systemagent_early_init(void)
{
u32 capid0_a;
u32 deven;
@ -179,8 +209,11 @@ void sandybridge_early_initialization(void)
/* Setup all BARs required for early PCIe and raminit */
sandybridge_setup_bars();
/* Set C0000-FFFFF to access RAM on both reads and writes */
enable_pam_region();
/* Setup IOMMU BARs */
sandybridge_init_iommu();
systemagent_vtd_init();
/* Device Enable, don't touch PEG bits */
deven = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN) | DEVEN_IGD;

48
src/northbridge/intel/sandybridge/iommu.c
View File

@ -1,48 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015 secunet Security Networks AG
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <device/mmio.h>
#include <device/pci_ops.h>
#include <device/device.h>
#include <device/pci_def.h>
#include "sandybridge.h"
void sandybridge_init_iommu(void)
{
const u32 capid0_a = pci_read_config32(PCI_DEV(0, 0, 0), 0xe4);
if (capid0_a & (1 << 23))
return;
/* setup BARs */
MCHBAR32(0x5404) = IOMMU_BASE1 >> 32;
MCHBAR32(0x5400) = IOMMU_BASE1 | 1;
MCHBAR32(0x5414) = IOMMU_BASE2 >> 32;
MCHBAR32(0x5410) = IOMMU_BASE2 | 1;
/* lock policies */
write32((void *)(IOMMU_BASE1 + 0xff0), 0x80000000);
const struct device *const azalia = pcidev_on_root(0x1b, 0);
if (azalia && azalia->enabled) {
write32((void *)(IOMMU_BASE2 + 0xff0), 0x20000000);
write32((void *)(IOMMU_BASE2 + 0xff0), 0xa0000000);
} else {
write32((void *)(IOMMU_BASE2 + 0xff0), 0x80000000);
}
}

4
src/northbridge/intel/sandybridge/romstage.c
View File

@ -74,8 +74,8 @@ void mainboard_romstage_entry(unsigned long bist)
/* Perform some early chipset initialization required
* before RAM initialization can work
*/
sandybridge_early_initialization();
printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
systemagent_early_init();
printk(BIOS_DEBUG, "Back from systemagent_early_init()\n");
s3resume = southbridge_detect_s3_resume();

2
src/northbridge/intel/sandybridge/sandybridge.h
View File

@ -216,7 +216,7 @@ static inline void barrier(void) { asm("" ::: "memory"); }
void intel_sandybridge_finalize_smm(void);
#else /* !__SMM__ */
int bridge_silicon_revision(void);
void sandybridge_early_initialization(void);
void systemagent_early_init(void);
void sandybridge_init_iommu(void);
void sandybridge_late_initialization(void);
void northbridge_romstage_finalize(int s3resume);