soc/intel/skylake: Use PCH_DEV_* instead of PCH_DEVFN_*
This change allows the same functions to be used across ramstage and smm without having to add checks for what stage is using it. BUG=b:67874513 Change-Id: I3b10c9e8975e8622d8cb0f66d90d39a914ba7e1c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -170,7 +170,7 @@ static bool pch_xhci_update_wake_event(device_t dev)
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}
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struct pme_status_info {
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int devfn;
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device_t dev;
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uint8_t reg_offset;
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uint32_t elog_event;
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};
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@ -184,7 +184,7 @@ static void pch_log_add_elog_event(const struct pme_status_info *info,
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* If wake source is XHCI, check for detailed wake source events on
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* USB2/3 ports.
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*/
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if ((info->devfn == PCH_DEVFN_XHCI) && pch_xhci_update_wake_event(dev))
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if ((info->dev == PCH_DEV_XHCI) && pch_xhci_update_wake_event(dev))
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return;
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elog_add_event_wake(info->elog_event, 0);
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@ -197,18 +197,17 @@ static void pch_log_pme_internal_wake_source(void)
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uint16_t val;
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bool dev_found = false;
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static const struct pme_status_info pme_status_info[] = {
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{ PCH_DEVFN_HDA, 0x54, ELOG_WAKE_SOURCE_PME_HDA },
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{ PCH_DEVFN_GBE, 0xcc, ELOG_WAKE_SOURCE_PME_GBE },
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{ PCH_DEVFN_SATA, 0x74, ELOG_WAKE_SOURCE_PME_SATA },
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{ PCH_DEVFN_CSE, 0x54, ELOG_WAKE_SOURCE_PME_CSE },
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{ PCH_DEVFN_XHCI, 0x74, ELOG_WAKE_SOURCE_PME_XHCI },
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{ PCH_DEVFN_USBOTG, 0x84, ELOG_WAKE_SOURCE_PME_XDCI },
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struct pme_status_info pme_status_info[] = {
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{ PCH_DEV_HDA, 0x54, ELOG_WAKE_SOURCE_PME_HDA },
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{ PCH_DEV_GBE, 0xcc, ELOG_WAKE_SOURCE_PME_GBE },
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{ PCH_DEV_SATA, 0x74, ELOG_WAKE_SOURCE_PME_SATA },
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{ PCH_DEV_CSE, 0x54, ELOG_WAKE_SOURCE_PME_CSE },
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{ PCH_DEV_XHCI, 0x74, ELOG_WAKE_SOURCE_PME_XHCI },
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{ PCH_DEV_USBOTG, 0x84, ELOG_WAKE_SOURCE_PME_XDCI },
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};
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for (i = 0; i < ARRAY_SIZE(pme_status_info); i++) {
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dev = dev_find_slot(0, pme_status_info[i].devfn);
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dev = pme_status_info[i].dev;
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if (!dev)
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continue;
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@ -232,23 +231,23 @@ static void pch_log_rp_wake_source(void)
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device_t dev;
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uint32_t val;
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static const struct pme_status_info pme_status_info[] = {
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{ PCH_DEVFN_PCIE1, 0x60, ELOG_WAKE_SOURCE_PME_PCIE1 },
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{ PCH_DEVFN_PCIE2, 0x60, ELOG_WAKE_SOURCE_PME_PCIE2 },
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{ PCH_DEVFN_PCIE3, 0x60, ELOG_WAKE_SOURCE_PME_PCIE3 },
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{ PCH_DEVFN_PCIE4, 0x60, ELOG_WAKE_SOURCE_PME_PCIE4 },
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{ PCH_DEVFN_PCIE5, 0x60, ELOG_WAKE_SOURCE_PME_PCIE5 },
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{ PCH_DEVFN_PCIE6, 0x60, ELOG_WAKE_SOURCE_PME_PCIE6 },
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{ PCH_DEVFN_PCIE7, 0x60, ELOG_WAKE_SOURCE_PME_PCIE7 },
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{ PCH_DEVFN_PCIE8, 0x60, ELOG_WAKE_SOURCE_PME_PCIE8 },
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{ PCH_DEVFN_PCIE9, 0x60, ELOG_WAKE_SOURCE_PME_PCIE9 },
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{ PCH_DEVFN_PCIE10, 0x60, ELOG_WAKE_SOURCE_PME_PCIE10 },
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{ PCH_DEVFN_PCIE11, 0x60, ELOG_WAKE_SOURCE_PME_PCIE11 },
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{ PCH_DEVFN_PCIE12, 0x60, ELOG_WAKE_SOURCE_PME_PCIE12 },
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struct pme_status_info pme_status_info[] = {
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{ PCH_DEV_PCIE1, 0x60, ELOG_WAKE_SOURCE_PME_PCIE1 },
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{ PCH_DEV_PCIE2, 0x60, ELOG_WAKE_SOURCE_PME_PCIE2 },
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{ PCH_DEV_PCIE3, 0x60, ELOG_WAKE_SOURCE_PME_PCIE3 },
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{ PCH_DEV_PCIE4, 0x60, ELOG_WAKE_SOURCE_PME_PCIE4 },
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{ PCH_DEV_PCIE5, 0x60, ELOG_WAKE_SOURCE_PME_PCIE5 },
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{ PCH_DEV_PCIE6, 0x60, ELOG_WAKE_SOURCE_PME_PCIE6 },
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{ PCH_DEV_PCIE7, 0x60, ELOG_WAKE_SOURCE_PME_PCIE7 },
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{ PCH_DEV_PCIE8, 0x60, ELOG_WAKE_SOURCE_PME_PCIE8 },
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{ PCH_DEV_PCIE9, 0x60, ELOG_WAKE_SOURCE_PME_PCIE9 },
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{ PCH_DEV_PCIE10, 0x60, ELOG_WAKE_SOURCE_PME_PCIE10 },
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{ PCH_DEV_PCIE11, 0x60, ELOG_WAKE_SOURCE_PME_PCIE11 },
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{ PCH_DEV_PCIE12, 0x60, ELOG_WAKE_SOURCE_PME_PCIE12 },
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};
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for (i = 0; i < ARRAY_SIZE(pme_status_info); i++) {
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dev = dev_find_slot(0, pme_status_info[i].devfn);
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dev = pme_status_info[i].dev;
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if (!dev)
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continue;
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