GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel/tigerlake: Support ISH 

Add ACPI Object for ISH SSDT
Enable/disable ISH based on devicetree

BRANCH=none
BUG=b:145946347
TEST=boot to OS with TGL RVP UP3

Signed-off-by: Hu, Hebo <hebo.hu@intel.com>
Signed-off-by: li feng <li1.feng@intel.com>
Change-Id: I30f4d936ece139cf67640e6df6a9f47579f87bca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
This commit is contained in:
li feng 2020-03-12 16:09:53 -07:00 committed by Patrick Georgi
parent b159d443dd
commit 2cf9d3883c
4 changed files with 33 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
src/soc/intel/tigerlake/acpi/ish.asl Normal file
View File

@ -0,0 +1,22 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2019 Google LLC.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* Intel Integrated Sensor Hub Controller 0:12.0 */
Device (ISHB)
{
Name (_ADR, 0x00120000)
Name (_DDN, "Integrated Sensor Hub Controller")
}

3
src/soc/intel/tigerlake/acpi/southbridge.asl
View File

@ -49,6 +49,9 @@
/* SMBus 0:1f.4 */
#include "smbus.asl"
/* ISH 0:12.0 */
#include "ish.asl"
/* USB XHCI 0:14.0 */
#include "xhci.asl"

1
src/soc/intel/tigerlake/chip.c
View File

@ -71,6 +71,7 @@ const char *soc_acpi_name(const struct device *dev)
switch (dev->path.pci.devfn) {
case SA_DEVFN_ROOT: return "MCHC";
case PCH_DEVFN_ISH: return "ISHB";
case PCH_DEVFN_XHCI: return "XHCI";
case PCH_DEVFN_I2C0: return "I2C0";
case PCH_DEVFN_I2C1: return "I2C1";

7
src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
View File

@ -89,6 +89,13 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
else
m_cfg->InternalGfx = 0x1;
/* ISH */
dev = pcidev_path_on_root(PCH_DEVFN_ISH);
if (!dev || !dev->enabled)
m_cfg->PchIshEnable = 0;
else
m_cfg->PchIshEnable = 1;
/* DP port config */
m_cfg->DdiPortAConfig = config->DdiPortAConfig;
m_cfg->DdiPortBConfig = config->DdiPortBConfig;