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nb/intel/pineview: Increase MMCONF decoding to 256 busses 

Linux kernel detects 256 busses but previously only 64 were
allocated.  Removes warning in OS.

Change-Id: Id83c85e60025a04acbe6a53dfea6878222d8791f
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/13033
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Damien Zammit 2016-01-18 16:39:51 +11:00 committed by Martin Roth
parent b8f8cdbd9e
commit 2cfab90baa
2 changed files with 4 additions and 2 deletions
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2
src/northbridge/intel/pineview/acpi/pineview.asl
View File

@ -33,7 +33,7 @@ Device (PDRC)
Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000)
Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_PCIEXBAR, 0x04000000)
Memory32Fixed(ReadWrite, DEFAULT_PCIEXBAR, 0x10000000)
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) /* Misc ICH */
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) /* Misc ICH */
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) /* Misc ICH */

4
src/northbridge/intel/pineview/bootblock.c
View File

@ -1,8 +1,10 @@
#include <arch/io.h>
#define PCIEXBAR 0x60
#define MMCONF_256_BUSSES 16
#define ENABLE 1
static void bootblock_northbridge_init(void)
{
pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR,
CONFIG_MMCONF_BASE_ADDRESS | 4 | 1);
CONFIG_MMCONF_BASE_ADDRESS | MMCONF_256_BUSSES | ENABLE);
}