nb/intel/pineview: Increase MMCONF decoding to 256 busses
Linux kernel detects 256 busses but previously only 64 were allocated. Removes warning in OS. Change-Id: Id83c85e60025a04acbe6a53dfea6878222d8791f Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/13033 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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@ -33,7 +33,7 @@ Device (PDRC)
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Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000)
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Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000)
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Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000)
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Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000)
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Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)
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Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)
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Memory32Fixed(ReadWrite, DEFAULT_PCIEXBAR, 0x04000000)
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Memory32Fixed(ReadWrite, DEFAULT_PCIEXBAR, 0x10000000)
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Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) /* Misc ICH */
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Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) /* Misc ICH */
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Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) /* Misc ICH */
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Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) /* Misc ICH */
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Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) /* Misc ICH */
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Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) /* Misc ICH */
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@ -1,8 +1,10 @@
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#include <arch/io.h>
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#include <arch/io.h>
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#define PCIEXBAR 0x60
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#define PCIEXBAR 0x60
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#define MMCONF_256_BUSSES 16
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#define ENABLE 1
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static void bootblock_northbridge_init(void)
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static void bootblock_northbridge_init(void)
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{
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{
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pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR,
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pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR,
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CONFIG_MMCONF_BASE_ADDRESS | 4 | 1);
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CONFIG_MMCONF_BASE_ADDRESS | MMCONF_256_BUSSES | ENABLE);
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}
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}
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