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soc/intel/apollolake: Add config option for enabling hotplug 

PcieRpHotPlug in apollolake UPD is default enabled. This change adds a
config option to enable hotplug only if explicitly requested by
mainboard. This changes the default behavior on all apollolake boards
to have hotplug disabled.

BUG=b:74633273
BRANCH=reef,coral

Change-Id: I572c054d31aaf5d43a79c4b1773ec9356da48d9d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Furquan Shaikh 2018-03-14 21:43:04 -07:00
parent 6d5e10c05d
commit 2cfc862a3e
2 changed files with 6 additions and 0 deletions
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3
src/soc/intel/apollolake/chip.c
View File

@ -534,6 +534,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
memcpy(silconfig->PcieRpClkReqNumber, cfg->pcie_rp_clkreq_pin, memcpy(silconfig->PcieRpClkReqNumber, cfg->pcie_rp_clkreq_pin,
sizeof(silconfig->PcieRpClkReqNumber)); sizeof(silconfig->PcieRpClkReqNumber));
memcpy(silconfig->PcieRpHotPlug, cfg->pcie_rp_hotplug_enable,
sizeof(silconfig->PcieRpHotPlug));
if (cfg->emmc_tx_cmd_cntl != 0) if (cfg->emmc_tx_cmd_cntl != 0)
silconfig->EmmcTxCmdCntl = cfg->emmc_tx_cmd_cntl; silconfig->EmmcTxCmdCntl = cfg->emmc_tx_cmd_cntl;
if (cfg->emmc_tx_data_cntl1 != 0) if (cfg->emmc_tx_data_cntl1 != 0)

3
src/soc/intel/apollolake/chip.h
View File

@ -46,6 +46,9 @@ struct soc_intel_apollolake_config {
*/ */
uint8_t pcie_rp_clkreq_pin[MAX_PCIE_PORTS]; uint8_t pcie_rp_clkreq_pin[MAX_PCIE_PORTS];
/* Enable/disable hot-plug for root ports (0 = disable, 1 = enable). */
uint8_t pcie_rp_hotplug_enable[MAX_PCIE_PORTS];
/* [14:8] DDR mode Number of dealy elements.Each = 125pSec. /* [14:8] DDR mode Number of dealy elements.Each = 125pSec.
* [6:0] SDR mode Number of dealy elements.Each = 125pSec. * [6:0] SDR mode Number of dealy elements.Each = 125pSec.
*/ */