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soc/amd/picasso,stoneyridge/mca: factor out mca_print_error() 

Change-Id: I7cd05a389c34c2e5f3d0ab4cd06d60a7e3e5cad9
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56239
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held 2021-07-12 22:10:24 +02:00
parent 82af7491c2
commit 2d0346a521
2 changed files with 42 additions and 37 deletions
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40
src/soc/amd/picasso/mca.c
View File

@ -145,6 +145,25 @@ static const char *const mca_bank_name[] = {
"L3 cache unit" "L3 cache unit"
}; };
static void mca_print_error(unsigned int bank)
{
msr_t msr;
printk(BIOS_WARNING, "#MC Error: core %u, bank %u %s\n", initial_lapicid(), bank,
bank < ARRAY_SIZE(mca_bank_name) ? mca_bank_name[bank] : "");
msr = rdmsr(MCAX_STATUS_MSR(bank));
printk(BIOS_WARNING, " MC%u_STATUS = %08x_%08x\n", bank, msr.hi, msr.lo);
msr = rdmsr(MCAX_ADDR_MSR(bank));
printk(BIOS_WARNING, " MC%u_ADDR = %08x_%08x\n", bank, msr.hi, msr.lo);
msr = rdmsr(MCAX_MISC0_MSR(bank));
printk(BIOS_WARNING, " MC%u_MISC = %08x_%08x\n", bank, msr.hi, msr.lo);
msr = rdmsr(MCAX_CTL_MSR(bank));
printk(BIOS_WARNING, " MC%u_CTL = %08x_%08x\n", bank, msr.hi, msr.lo);
msr = rdmsr(MCA_CTL_MASK_MSR(bank));
printk(BIOS_WARNING, " MC%u_CTL_MASK = %08x_%08x\n", bank, msr.hi, msr.lo);
}
/* Check the Machine Check Architecture Extension registers */ /* Check the Machine Check Architecture Extension registers */
void check_mca(void) void check_mca(void)
{ {
@ -154,28 +173,11 @@ void check_mca(void)
const unsigned int num_banks = mca_get_bank_count(); const unsigned int num_banks = mca_get_bank_count();
for (i = 0 ; i < num_banks ; i++) { for (i = 0 ; i < num_banks ; i++) {
mci.bank = i;
mci.sts = rdmsr(MCAX_STATUS_MSR(i)); mci.sts = rdmsr(MCAX_STATUS_MSR(i));
if (mci.sts.hi || mci.sts.lo) { if (mci.sts.hi || mci.sts.lo) {
printk(BIOS_WARNING, "#MC Error: core %u, bank %u %s\n", mca_print_error(i);
initial_lapicid(), i,
i < ARRAY_SIZE(mca_bank_name) ? mca_bank_name[i] : "");
printk(BIOS_WARNING, " MC%u_STATUS = %08x_%08x\n",
i, mci.sts.hi, mci.sts.lo);
msr = rdmsr(MCAX_ADDR_MSR(i));
printk(BIOS_WARNING, " MC%u_ADDR = %08x_%08x\n",
i, msr.hi, msr.lo);
msr = rdmsr(MCAX_MISC0_MSR(i));
printk(BIOS_WARNING, " MC%u_MISC = %08x_%08x\n",
i, msr.hi, msr.lo);
msr = rdmsr(MCAX_CTL_MSR(i));
printk(BIOS_WARNING, " MC%u_CTL = %08x_%08x\n",
i, msr.hi, msr.lo);
msr = rdmsr(MCA_CTL_MASK_MSR(i));
printk(BIOS_WARNING, " MC%u_CTL_MASK = %08x_%08x\n",
i, msr.hi, msr.lo);
mci.bank = i;
if (CONFIG(ACPI_BERT) && mca_valid(mci.sts)) if (CONFIG(ACPI_BERT) && mca_valid(mci.sts))
build_bert_mca_error(&mci); build_bert_mca_error(&mci);
} }

39
src/soc/amd/stoneyridge/mca.c
View File

@ -145,6 +145,25 @@ static const char *const mca_bank_name[] = {
"Floating point unit" "Floating point unit"
}; };
static void mca_print_error(unsigned int bank)
{
msr_t msr;
printk(BIOS_WARNING, "#MC Error: core %u, bank %u %s\n", initial_lapicid(), bank,
mca_bank_name[bank]);
msr = rdmsr(IA32_MC0_STATUS + (bank * 4));
printk(BIOS_WARNING, " MC%u_STATUS = %08x_%08x\n", bank, msr.hi, msr.lo);
msr = rdmsr(IA32_MC0_ADDR + (bank * 4));
printk(BIOS_WARNING, " MC%u_ADDR = %08x_%08x\n", bank, msr.hi, msr.lo);
msr = rdmsr(IA32_MC0_MISC + (bank * 4));
printk(BIOS_WARNING, " MC%u_MISC = %08x_%08x\n", bank, msr.hi, msr.lo);
msr = rdmsr(IA32_MC0_CTL + (bank * 4));
printk(BIOS_WARNING, " MC%u_CTL = %08x_%08x\n", bank, msr.hi, msr.lo);
msr = rdmsr(MC0_CTL_MASK + bank);
printk(BIOS_WARNING, " MC%u_CTL_MASK = %08x_%08x\n", bank, msr.hi, msr.lo);
}
void check_mca(void) void check_mca(void)
{ {
unsigned int i; unsigned int i;
@ -157,27 +176,11 @@ void check_mca(void)
if (i == 3) /* Reserved in Family 15h */ if (i == 3) /* Reserved in Family 15h */
continue; continue;
mci.bank = i;
mci.sts = rdmsr(IA32_MC0_STATUS + (i * 4)); mci.sts = rdmsr(IA32_MC0_STATUS + (i * 4));
if (mci.sts.hi || mci.sts.lo) { if (mci.sts.hi || mci.sts.lo) {
printk(BIOS_WARNING, "#MC Error: core %u, bank %u %s\n", mca_print_error(i);
initial_lapicid(), i, mca_bank_name[i]);
printk(BIOS_WARNING, " MC%u_STATUS = %08x_%08x\n",
i, mci.sts.hi, mci.sts.lo);
msr = rdmsr(IA32_MC0_ADDR + (i * 4));
printk(BIOS_WARNING, " MC%u_ADDR = %08x_%08x\n",
i, msr.hi, msr.lo);
msr = rdmsr(IA32_MC0_MISC + (i * 4));
printk(BIOS_WARNING, " MC%u_MISC = %08x_%08x\n",
i, msr.hi, msr.lo);
msr = rdmsr(IA32_MC0_CTL + (i * 4));
printk(BIOS_WARNING, " MC%u_CTL = %08x_%08x\n",
i, msr.hi, msr.lo);
msr = rdmsr(MC0_CTL_MASK + i);
printk(BIOS_WARNING, " MC%u_CTL_MASK = %08x_%08x\n",
i, msr.hi, msr.lo);
mci.bank = i;
if (CONFIG(ACPI_BERT) && mca_valid(mci.sts)) if (CONFIG(ACPI_BERT) && mca_valid(mci.sts))
build_bert_mca_error(&mci); build_bert_mca_error(&mci);
} }