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soc/intel/denverton_ns: Fill dimm info for SMBIOS table 17 

Rework display_fsp_smbios_memory_info_hob (shared code).

Import code to convert memory HOB to dimm info for SMBIOS table 17
mostly copied from fsp1_1 mainboard_save_dimm_info.

Change-Id: Id5c4ceaf4e65359f72ec764f0914b5daa82f257e
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23851
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Julien Viard de Galbert 2018-02-26 18:32:59 +01:00 committed by Martin Roth
parent ad126109ca
commit 2d0aaa7fc1
7 changed files with 253 additions and 58 deletions
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1
src/soc/intel/denverton_ns/Makefile.inc
View File

@ -63,6 +63,7 @@ ramstage-y += cpu.c
ramstage-y += tsc_freq.c
ramstage-y += spi.c
ramstage-y += fiamux.c
ramstage-y += hob_mem.c
ramstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c

7
src/soc/intel/denverton_ns/chip.c
View File

@ -32,6 +32,7 @@
#include <soc/ramstage.h>
#include <soc/fiamux.h>
#include <spi-generic.h>
#include <soc/hob_mem.h>
static void pci_domain_set_resources(device_t dev)
{
@ -64,7 +65,11 @@ static void soc_enable_dev(device_t dev)
dev->ops = &cpu_bus_ops;
}
static void soc_init(void *data) { fsp_silicon_init(false); }
static void soc_init(void *data)
{
fsp_silicon_init(false);
soc_save_dimm_info();
}
static void soc_final(void *data) {}

48
src/soc/intel/denverton_ns/hob_display.c
View File

@ -17,6 +17,7 @@
#include <console/console.h>
#include <fsp/util.h>
#include <lib.h>
#include <soc/hob_mem.h>
static const uint8_t fsp_hob_resource_owner_graphics_guid[16] = {
0xa7, 0x3a, 0x7c, 0x9c, 0x32, 0x55, 0x17, 0x49,
@ -69,3 +70,50 @@ void soc_display_hob(const struct hob_header *hob)
{
hexdump(hob, hob->length);
}
void soc_display_fsp_smbios_memory_info_hob(
const FSP_SMBIOS_MEMORY_INFO *memory_info_hob)
{
int channel, dimm;
const DIMM_INFO *dimm_info;
const CHANNEL_INFO *channel_info;
/* Display the data in the FSP_SMBIOS_MEMORY_INFO HOB */
printk(BIOS_DEBUG, "FSP_SMBIOS_MEMORY_INFO HOB\n");
printk(BIOS_DEBUG, " 0x%02x: Revision\n",
memory_info_hob->Revision);
printk(BIOS_DEBUG, " 0x%02x: MemoryType\n",
memory_info_hob->MemoryType);
printk(BIOS_DEBUG, " %d: MemoryFrequencyInMHz\n",
memory_info_hob->MemoryFrequencyInMHz);
printk(BIOS_DEBUG, " %d: DataWidth in bits\n",
memory_info_hob->DataWidth);
printk(BIOS_DEBUG, " 0x%02x: ErrorCorrectionType\n",
memory_info_hob->ErrorCorrectionType);
printk(BIOS_DEBUG, " 0x%02x: ChannelCount\n",
memory_info_hob->ChannelCount);
for (channel = 0; channel < memory_info_hob->ChannelCount;
channel++) {
channel_info = &memory_info_hob->ChannelInfo[channel];
printk(BIOS_DEBUG, " Channel %d\n", channel);
printk(BIOS_DEBUG, " 0x%02x: ChannelId\n",
channel_info->ChannelId);
printk(BIOS_DEBUG, " 0x%02x: DimmCount\n",
channel_info->DimmCount);
for (dimm = 0; dimm < channel_info->DimmCount;
dimm++) {
dimm_info = &channel_info->DimmInfo[dimm];
printk(BIOS_DEBUG, " DIMM %d\n", dimm);
printk(BIOS_DEBUG, " 0x%02x: DimmId\n",
dimm_info->DimmId);
printk(BIOS_DEBUG, " %d: SizeInMb\n",
dimm_info->SizeInMb);
printk(BIOS_DEBUG, " 0x%04x: MfgId\n",
dimm_info->MfgId);
printk(BIOS_DEBUG, "%*.*s: ModulePartNum\n",
(int)sizeof(dimm_info->ModulePartNum),
(int)sizeof(dimm_info->ModulePartNum),
dimm_info->ModulePartNum);
}
}
}

135
src/soc/intel/denverton_ns/hob_mem.c Normal file
View File

@ -0,0 +1,135 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
* Copyright (C) 2015-2016 Intel Corporation.
* Copyright (C) 2017-2018 Online SAS.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <cbmem.h>
#include <console/console.h>
#include <string.h>
#include <soc/hob_mem.h>
#include <smbios.h>
#include <memory_info.h>
#include <soc/ramstage.h>
/* Save the DIMM information for SMBIOS table 17 */
void soc_save_dimm_info(void)
{
int channel;
const CHANNEL_INFO *channel_info;
int dimm;
const DIMM_INFO *dimm_info;
int dimm_max;
int index;
struct memory_info *mem_info;
const FSP_SMBIOS_MEMORY_INFO *memory_info_hob;
/* Get the memory info HOB */
memory_info_hob = soc_get_fsp_smbios_memory_info_hob();
if (memory_info_hob == NULL)
return;
/* Display the data in the FSP_SMBIOS_MEMORY_INFO HOB */
if (IS_ENABLED(CONFIG_DISPLAY_HOBS))
soc_display_fsp_smbios_memory_info_hob(memory_info_hob);
/*
* Allocate CBMEM area for DIMM information used to populate SMBIOS
* table 17
*/
mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info));
printk(BIOS_DEBUG, "CBMEM entry for DIMM info: 0x%p\n", mem_info);
if (mem_info == NULL)
return;
memset(mem_info, 0, sizeof(*mem_info));
/* Describe the first N DIMMs in the system */
index = 0;
dimm_max = ARRAY_SIZE(mem_info->dimm);
for (channel = 0; channel < memory_info_hob->ChannelCount; channel++) {
if (index >= dimm_max)
break;
channel_info = &memory_info_hob->ChannelInfo[channel];
for (dimm = 0; dimm < channel_info->DimmCount; dimm++) {
if (index >= dimm_max)
break;
dimm_info = &channel_info->DimmInfo[dimm];
/* Populate the DIMM information */
if (!dimm_info->SizeInMb)
continue;
mem_info->dimm[index].dimm_size =
dimm_info->SizeInMb;
mem_info->dimm[index].ddr_type =
memory_info_hob->MemoryType;
mem_info->dimm[index].ddr_frequency =
memory_info_hob->MemoryFrequencyInMHz;
mem_info->dimm[index].channel_num =
channel_info->ChannelId;
mem_info->dimm[index].dimm_num =
dimm_info->DimmId;
strncpy((char *)
mem_info->dimm[index].module_part_number,
(char *)dimm_info->ModulePartNum, 18);
mem_info->dimm[index].mod_id =
dimm_info->MfgId;
switch (memory_info_hob->DataWidth) {
default:
case 8:
mem_info->dimm[index].bus_width =
MEMORY_BUS_WIDTH_8;
break;
case 16:
mem_info->dimm[index].bus_width =
MEMORY_BUS_WIDTH_16;
break;
case 32:
mem_info->dimm[index].bus_width =
MEMORY_BUS_WIDTH_32;
break;
case 64:
mem_info->dimm[index].bus_width =
MEMORY_BUS_WIDTH_64;
break;
case 128:
mem_info->dimm[index].bus_width =
MEMORY_BUS_WIDTH_128;
break;
}
/* Add any mainboard specific information */
mainboard_add_dimm_info(mem_info, channel, dimm, index);
index++;
}
}
mem_info->dimm_cnt = index;
printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt);
}
/* Add any mainboard specific information */
__attribute__((weak)) void mainboard_add_dimm_info(struct memory_info *mem_info,
int channel, int dimm,
int index)
{
printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
}

55
src/soc/intel/denverton_ns/include/soc/hob_mem.h Normal file
View File

@ -0,0 +1,55 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
* Copyright (C) 2015-2016 Intel Corporation.
* Copyright (C) 2017-2018 Online SAS.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _DENVERTON_NS_HOB_MEM_H
#define _DENVERTON_NS_HOB_MEM_H
#include <fsp/util.h>
void soc_display_fsp_smbios_memory_info_hob(
const FSP_SMBIOS_MEMORY_INFO *memory_info_hob);
void soc_save_dimm_info(void);
#define FSP_SMBIOS_MEMORY_INFO_GUID \
{ \
0x8c, 0x10, 0xa1, 0x01, 0xee, 0x9d, 0x84, 0x49, \
0x88, 0xc3, 0xee, 0xe8, 0xc4, 0x9e, 0xfb, 0x89 \
}
static inline const FSP_SMBIOS_MEMORY_INFO *
soc_get_fsp_smbios_memory_info_hob(void)
{
size_t hob_size;
const FSP_SMBIOS_MEMORY_INFO *memory_info_hob;
const uint8_t smbios_memory_info_guid[16] =
FSP_SMBIOS_MEMORY_INFO_GUID;
/* Locate the memory info HOB */
memory_info_hob = fsp_find_extension_hob_by_guid(
smbios_memory_info_guid,
&hob_size);
if (memory_info_hob == NULL || hob_size == 0) {
printk(BIOS_ERR, "SMBIOS MEMORY_INFO_DATA_HOB not found\n");
return NULL;
}
return memory_info_hob;
}
#endif // _DENVERTON_NS_HOB_MEM_H

3
src/soc/intel/denverton_ns/include/soc/ramstage.h
View File

@ -19,10 +19,13 @@
#include <device/device.h>
#include <fsp/api.h>
#include <fsp/util.h>
#include <memory_info.h>
void denverton_init_cpus(device_t dev);
void mainboard_silicon_init_params(FSPS_UPD *params);
void southcluster_enable_dev(device_t dev);
void mainboard_add_dimm_info(struct memory_info *mem_info, int channel,
int dimm, int index);
extern struct pci_operations soc_pci_ops;

62
src/soc/intel/denverton_ns/romstage.c
View File

@ -28,74 +28,22 @@
#include <soc/smbus.h>
#include <soc/smm.h>
#include <soc/soc_util.h>
#include <soc/hob_mem.h>
void __weak mainboard_config_gpios(void) {}
#define FSP_SMBIOS_MEMORY_INFO_GUID \
{ \
0x8c, 0x10, 0xa1, 0x01, 0xee, 0x9d, 0x84, 0x49, \
0x88, 0xc3, 0xee, 0xe8, 0xc4, 0x9e, 0xfb, 0x89 \
}
#if IS_ENABLED(CONFIG_DISPLAY_HOBS)
static void display_fsp_smbios_memory_info_hob(void)
{
int channel, dimm;
size_t hob_size;
const DIMM_INFO *dimm_info;
const CHANNEL_INFO *channel_info;
const FSP_SMBIOS_MEMORY_INFO *memory_info_hob;
const uint8_t smbios_memory_info_guid[16] =
FSP_SMBIOS_MEMORY_INFO_GUID;
/* Locate the memory info HOB */
memory_info_hob = fsp_find_extension_hob_by_guid(
smbios_memory_info_guid,
&hob_size);
/* Get the memory info HOB */
memory_info_hob = soc_get_fsp_smbios_memory_info_hob();
if (memory_info_hob == NULL || hob_size == 0) {
printk(BIOS_ERR, "SMBIOS MEMORY_INFO_DATA_HOB not found\n");
if (memory_info_hob == NULL)
return;
}
/* Display the data in the FSP_SMBIOS_MEMORY_INFO HOB */
printk(BIOS_DEBUG, "FSP_SMBIOS_MEMORY_INFO HOB\n");
printk(BIOS_DEBUG, " 0x%02x: Revision\n",
memory_info_hob->Revision);
printk(BIOS_DEBUG, " 0x%02x: MemoryType\n",
memory_info_hob->MemoryType);
printk(BIOS_DEBUG, " %d: MemoryFrequencyInMHz\n",
memory_info_hob->MemoryFrequencyInMHz);
printk(BIOS_DEBUG, " %d: DataWidth in bits\n",
memory_info_hob->DataWidth);
printk(BIOS_DEBUG, " 0x%02x: ErrorCorrectionType\n",
memory_info_hob->ErrorCorrectionType);
printk(BIOS_DEBUG, " 0x%02x: ChannelCount\n",
memory_info_hob->ChannelCount);
for (channel = 0; channel < memory_info_hob->ChannelCount;
channel++) {
channel_info = &memory_info_hob->ChannelInfo[channel];
printk(BIOS_DEBUG, " Channel %d\n", channel);
printk(BIOS_DEBUG, " 0x%02x: ChannelId\n",
channel_info->ChannelId);
printk(BIOS_DEBUG, " 0x%02x: DimmCount\n",
channel_info->DimmCount);
for (dimm = 0; dimm < channel_info->DimmCount;
dimm++) {
dimm_info = &channel_info->DimmInfo[dimm];
printk(BIOS_DEBUG, " DIMM %d\n", dimm);
printk(BIOS_DEBUG, " 0x%02x: DimmId\n",
dimm_info->DimmId);
printk(BIOS_DEBUG, " %d: SizeInMb\n",
dimm_info->SizeInMb);
printk(BIOS_DEBUG, " 0x%04x: MfgId\n",
dimm_info->MfgId);
printk(BIOS_DEBUG, "%*.*s: ModulePartNum\n",
(int)sizeof(dimm_info->ModulePartNum),
(int)sizeof(dimm_info->ModulePartNum),
dimm_info->ModulePartNum);
}
}
soc_display_fsp_smbios_memory_info_hob(memory_info_hob);
}
#endif