Add ASUS DSBF mainboard
Change-Id: Iad38b92ca3a582e5aec07b92c994bfbe78b09855 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1223 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
Sven Schnelle
Patrick Georgi
parent
6fa1d3a218
commit
2d0d83c3dd
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@ -59,7 +59,8 @@ config BOARD_ASUS_P2B_LS
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bool "P2B-LS"
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bool "P2B-LS"
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config BOARD_ASUS_P3B_F
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config BOARD_ASUS_P3B_F
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bool "P3B-F"
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bool "P3B-F"
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config BOARD_ASUS_DSBF
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bool "DSBF"
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endchoice
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endchoice
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source "src/mainboard/asus/a8n_e/Kconfig"
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source "src/mainboard/asus/a8n_e/Kconfig"
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@ -81,6 +82,7 @@ source "src/mainboard/asus/p2b-ds/Kconfig"
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source "src/mainboard/asus/p2b-f/Kconfig"
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source "src/mainboard/asus/p2b-f/Kconfig"
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source "src/mainboard/asus/p2b-ls/Kconfig"
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source "src/mainboard/asus/p2b-ls/Kconfig"
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source "src/mainboard/asus/p3b-f/Kconfig"
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source "src/mainboard/asus/p3b-f/Kconfig"
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source "src/mainboard/asus/dsbf/Kconfig
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config MAINBOARD_VENDOR
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config MAINBOARD_VENDOR
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string
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string
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@ -0,0 +1,45 @@
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if BOARD_ASUS_DSBF
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select ARCH_X86
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select CPU_INTEL_SOCKET_LGA771
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select SOUTHBRIDGE_INTEL_I3100
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select NORTHBRIDGE_INTEL_I5000
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select SUPERIO_WINBOND_W83627HF
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select MMCONF_SUPPORT
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select BOARD_ROMSIZE_KB_512
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select HAVE_MP_TABLE
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select HAVE_PIRQ_TABLE
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select DRIVERS_I2C_W83793
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select DRIVERS_GENERIC_IOAPIC
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config MAINBOARD_DIR
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string
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default asus/dsbf
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config DCACHE_RAM_BASE
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hex
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default 0xffdf8000
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config DCACHE_RAM_SIZE
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hex
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default 0x8000
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config MAINBOARD_PART_NUMBER
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string
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default "DSBF"
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config MMCONF_BASE_ADDRESS
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hex
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default 0xe0000000
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config IRQ_SLOT_COUNT
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int
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default 48
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config MAX_CPUS
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int
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default 8
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endif
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@ -0,0 +1,21 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (c) 2011 Sven Schnelle <svens@stackframe.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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extern struct chip_operations mainboard_ops;
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struct mainboard_config {};
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@ -0,0 +1,142 @@
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#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2007-2008 coresystems GmbH
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; version 2 of
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# the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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# MA 02110-1301 USA
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#
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# -----------------------------------------------------------------
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entries
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#start-bit length config config-ID name
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#0 8 r 0 seconds
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#8 8 r 0 alarm_seconds
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#16 8 r 0 minutes
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#24 8 r 0 alarm_minutes
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#32 8 r 0 hours
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#40 8 r 0 alarm_hours
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#48 8 r 0 day_of_week
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#56 8 r 0 day_of_month
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#64 8 r 0 month
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#72 8 r 0 year
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# -----------------------------------------------------------------
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# Status Register A
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#80 4 r 0 rate_select
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#84 3 r 0 REF_Clock
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#87 1 r 0 UIP
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# -----------------------------------------------------------------
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# Status Register B
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#88 1 r 0 auto_switch_DST
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#89 1 r 0 24_hour_mode
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#90 1 r 0 binary_values_enable
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#91 1 r 0 square-wave_out_enable
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#92 1 r 0 update_finished_enable
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#93 1 r 0 alarm_interrupt_enable
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#94 1 r 0 periodic_interrupt_enable
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#95 1 r 0 disable_clock_updates
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# -----------------------------------------------------------------
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# Status Register C
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#96 4 r 0 status_c_rsvd
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#100 1 r 0 uf_flag
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#101 1 r 0 af_flag
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#102 1 r 0 pf_flag
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#103 1 r 0 irqf_flag
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# -----------------------------------------------------------------
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# Status Register D
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#104 7 r 0 status_d_rsvd
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#111 1 r 0 valid_cmos_ram
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# -----------------------------------------------------------------
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# Diagnostic Status Register
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#112 8 r 0 diag_rsvd1
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# -----------------------------------------------------------------
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0 120 r 0 reserved_memory
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#120 264 r 0 unused
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# -----------------------------------------------------------------
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# RTC_BOOT_BYTE (coreboot hardcoded)
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384 1 e 4 boot_option
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385 1 e 4 last_boot
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388 4 r 0 reboot_bits
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#390 2 r 0 unused?
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# -----------------------------------------------------------------
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# coreboot config options: console
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392 3 e 5 baud_rate
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395 4 e 6 debug_level
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#399 1 r 0 unused
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# coreboot config options: cpu
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400 1 e 2 hyper_threading
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#401 7 r 0 unused
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# coreboot config options: southbridge
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408 1 e 1 nmi
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#409 2 e 7 power_on_after_fail
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#411 5 r 0 unused
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# coreboot config options: bootloader
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416 512 s 0 boot_devices
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928 8 h 0 boot_default
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936 1 e 8 cmos_defaults_loaded
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937 1 e 1 lpt
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#938 46 r 0 unused
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# coreboot config options: check sums
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984 16 h 0 check_sum
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# -----------------------------------------------------------------
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enumerations
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#ID value text
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1 0 Disable
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1 1 Enable
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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5 0 115200
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5 1 57600
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5 2 38400
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5 3 19200
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5 4 9600
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5 5 4800
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5 6 2400
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5 7 1200
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6 1 Emergency
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6 2 Alert
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6 3 Critical
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6 4 Error
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6 5 Warning
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6 6 Notice
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6 7 Info
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6 8 Debug
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6 9 Spew
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7 0 Disable
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7 1 Enable
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7 2 Keep
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8 0 No
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8 1 Yes
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9 0 Secondary
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9 1 Primary
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# -----------------------------------------------------------------
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checksums
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checksum 392 983 984
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@ -0,0 +1,185 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007-2009 coresystems GmbH
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## Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
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##
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## This program is free software; you can redistribute it and/or
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## modify it under the terms of the GNU General Public License as
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## published by the Free Software Foundation; version 2 of
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## the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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## MA 02110-1301 USA
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##
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chip northbridge/intel/i5000
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device lapic_cluster 0 on
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chip cpu/intel/socket_LGA771
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device lapic 0 on end
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end
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end
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device pci_domain 0 on
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device pci 00.0 on # Host bridge
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subsystemid 0x1043 0x81db
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end
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device pci 02.0 on # PCI Express x8 Port 2-3
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ioapic_irq 8 INTA 0x10
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ioapic_irq 8 INTB 0x11
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ioapic_irq 8 INTC 0x12
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ioapic_irq 8 INTD 0x13
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device pci 00.0 on # PCI Express Upstream Port
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device pci 00.0 on # PCI Express Downstream Port E1
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device pci 00.0 on # 6700PXH PCI Express-to-PCI Bridge A
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ioapic_irq 8 INTA 0x11
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ioapic_irq 8 INTB 0x10
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ioapic_irq 8 INTC 0x11
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ioapic_irq 8 INTD 0x10
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# PCI slot
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device pci 00.2 on # 6700PXH PCI Express-to-PCI Bridge B
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# PCI slot
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end
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end
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end
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device pci 00.1 on end
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device pci 00.3 on # PCI Express to PCI-X Bridge
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ioapic_irq 9 INTA 3
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ioapic_irq 9 INTB 0
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ioapic_irq 9 INTC 1
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ioapic_irq 9 INTD 2
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# PCI-X Slot
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end
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end
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end
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device pci 03.0 on
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ioapic_irq 8 INTA 0x10
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end
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device pci 04.0 on
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ioapic_irq 8 INTA 0x10
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end
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device pci 05.0 on
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ioapic_irq 8 INTA 0x10
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end
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device pci 06.0 on
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ioapic_irq 8 INTA 0x10
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end
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device pci 07.0 on
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ioapic_irq 8 INTA 0x10
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end
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device pci 10.0 on end # FBD
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device pci 10.1 on end # FBD
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device pci 10.2 on end # FBD
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device pci 11.0 on end # FBD reserved
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device pci 13.0 on end # FBD reserved
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device pci 15.0 on end # FBD
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device pci 16.0 on end # FBD
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chip drivers/generic/ioapic
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register "have_isa_interrupts" = "1"
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register "irq_on_fsb" = "1"
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register "enable_virtual_wire" = "1"
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register "base" = "0xfec00000"
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device ioapic 8 on end
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end
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chip drivers/generic/ioapic
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register "irq_on_fsb" = "1"
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register "base" = "0xfec80000"
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device ioapic 9 on end
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end
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chip southbridge/intel/i3100
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register "pirq_a_d" = "0x0b0b0b0b"
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register "pirq_e_h" = "0x80808080"
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register "sata_ports_implemented" = "0x3f"
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device pci 1c.0 on
|
||||||
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ioapic_irq 8 INTA 0x14
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||||||
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ioapic_irq 8 INTB 0x15
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||||||
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ioapic_irq 8 INTC 0x16
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ioapic_irq 8 INTD 0x17
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||||||
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end # PCIe bridge
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||||||
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device pci 1d.0 on
|
||||||
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ioapic_irq 8 INTA 0x10
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end # USB UHCI
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||||||
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device pci 1d.1 on
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||||||
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ioapic_irq 8 INTB 0x11
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||||||
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end # USB UHCI
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device pci 1d.2 on
|
||||||
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ioapic_irq 8 INTC 0x12
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||||||
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end # USB UHCI
|
||||||
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device pci 1d.3 on
|
||||||
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ioapic_irq 8 INTD 0x13
|
||||||
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end # USB UHCI
|
||||||
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device pci 1d.7 on end # USB2 EHCI
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||||||
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device pci 1e.0 on
|
||||||
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device pci 01.0 on end
|
||||||
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end
|
||||||
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|
||||||
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device pci 1f.0 on # PCI-LPC bridge
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||||||
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ioapic_irq 8 INTA 0x11
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||||||
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chip superio/winbond/w83627hf
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||||||
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device pnp 2e.0 off end # FDC
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device pnp 2e.1 on # Parallel Port
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io 0x60 = 0x378
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irq 0x70 = 7
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||||||
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end
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||||||
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device pnp 2e.2 on # Serial Port 1
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||||||
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io 0x60 = 0x3f8
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||||||
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irq 0x70 = 4
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||||||
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end
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||||||
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||||||
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device pnp 2e.3 off end
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||||||
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device pnp 2e.5 on # KBC
|
||||||
|
io 0x60 = 0x60
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io 0x62 = 0x64
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||||||
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irq 0x70 = 1
|
||||||
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irq 0x72 = 12
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||||||
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end
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||||||
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|
||||||
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device pnp 2e.6 off end # CIR
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||||||
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device pnp 2e.7 off end # Game port / MIDI
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||||||
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device pnp 2e.8 off end # GPIO2
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||||||
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device pnp 2e.9 on end # GPIO3
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||||||
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device pnp 2e.a on end # ACPI
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||||||
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device pnp 2e.b off end # HWMON
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||||||
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end
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||||||
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end
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||||||
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device pci 1f.1 off end # IDE
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||||||
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device pci 1f.2 on end # SATA
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||||||
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device pci 1f.3 on # SMBUS
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||||||
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chip drivers/i2c/w83793
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||||||
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register "mfc" = "0x28"
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||||||
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register "fanin" = "0x1f"
|
||||||
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register "peci_agent_conf" = "0x33"
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||||||
|
register "tcase0" = "0x5e"
|
||||||
|
register "tcase1" = "0x5e"
|
||||||
|
register "tcase2" = "0x5e"
|
||||||
|
register "tcase3" = "0x5e"
|
||||||
|
register "tr_enable" = "0x01"
|
||||||
|
register "critical_temperature" = "0x7f"
|
||||||
|
register "td1_fan_select" = "0x09"
|
||||||
|
register "td2_fan_select" = "0x09"
|
||||||
|
register "td3_fan_select" = "0x09"
|
||||||
|
register "td4_fan_select" = "0x09"
|
||||||
|
register "tr1_fan_select" = "0x09"
|
||||||
|
register "tr2_fan_select" = "0x09"
|
||||||
|
device i2c 0x2f on end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
@ -0,0 +1,57 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <arch/pirq_routing.h>
|
||||||
|
|
||||||
|
const struct irq_routing_table intel_irq_routing_table = {
|
||||||
|
PIRQ_SIGNATURE, /* u32 signature */
|
||||||
|
PIRQ_VERSION, /* u16 version */
|
||||||
|
32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */
|
||||||
|
0x00, /* Interrupt router bus */
|
||||||
|
(0x1f << 3) | 0x0, /* Interrupt router dev */
|
||||||
|
0, /* IRQs devoted exclusively to PCI usage */
|
||||||
|
0x8086, /* Vendor */
|
||||||
|
0x2670, /* Device */
|
||||||
|
0, /* Miniport */
|
||||||
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||||
|
0, /* Checksum (has to be set to some value that
|
||||||
|
* would give 0 after the sum of all bytes
|
||||||
|
* for this structure (including checksum).
|
||||||
|
*/
|
||||||
|
{
|
||||||
|
/* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
|
||||||
|
{0x00, (0x1c << 3) | 0x0, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0},
|
||||||
|
{0x00, (0x1c << 3) | 0x1, {{0x00, 0x0000}, {0x61, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0},
|
||||||
|
{0x00, (0x1c << 3) | 0x2, {{0x00, 0x0000}, {0x00, 0x0000}, {0x62, 0x1ef8}, {0x00, 0x0000}}, 0, 0},
|
||||||
|
{0x00, (0x1c << 3) | 0x3, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x63, 0x1ef8}}, 0, 0},
|
||||||
|
{0x00, (0x1d << 3) | 0x0, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0},
|
||||||
|
{0x00, (0x1d << 3) | 0x1, {{0x00, 0x0000}, {0x61, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0},
|
||||||
|
{0x00, (0x1d << 3) | 0x2, {{0x00, 0x0000}, {0x00, 0x0000}, {0x62, 0x1ef8}, {0x00, 0x0000}}, 0, 0},
|
||||||
|
{0x00, (0x1d << 3) | 0x3, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x63, 0x1ef8}}, 0, 0},
|
||||||
|
{0x00, (0x1d << 3) | 0x7, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0},
|
||||||
|
{0x00, (0x1f << 3) | 0x1, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0},
|
||||||
|
{0x00, (0x1f << 3) | 0x2, {{0x00, 0x0000}, {0x61, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0},
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||||
|
{
|
||||||
|
return copy_pirq_routing_table(addr);
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,41 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; version 2 of
|
||||||
|
* the License.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||||
|
* MA 02110-1301 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <console/console.h>
|
||||||
|
#include <device/device.h>
|
||||||
|
#include <arch/io.h>
|
||||||
|
#include <boot/tables.h>
|
||||||
|
#include <delay.h>
|
||||||
|
#include <arch/coreboot_tables.h>
|
||||||
|
#include "chip.h"
|
||||||
|
#include <device/pci_def.h>
|
||||||
|
#include <device/pci_ops.h>
|
||||||
|
#include <arch/io.h>
|
||||||
|
|
||||||
|
static void mainboard_enable(device_t dev)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
struct chip_operations mainboard_ops = {
|
||||||
|
CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER)
|
||||||
|
.enable_dev = mainboard_enable,
|
||||||
|
};
|
||||||
|
|
||||||
|
|
@ -0,0 +1,147 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2007-2009 coresystems GmbH
|
||||||
|
* Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; version 2 of
|
||||||
|
* the License.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||||
|
* MA 02110-1301 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
#include <string.h>
|
||||||
|
#include <arch/io.h>
|
||||||
|
#include <arch/romcc_io.h>
|
||||||
|
#include <device/pci_def.h>
|
||||||
|
#include <device/pnp_def.h>
|
||||||
|
#include <cpu/x86/lapic.h>
|
||||||
|
#include <lib.h>
|
||||||
|
#include <console/console.h>
|
||||||
|
#include <cpu/x86/bist.h>
|
||||||
|
#include <superio/winbond/w83627hf/early_serial.c>
|
||||||
|
#include <northbridge/intel/i5000/raminit.h>
|
||||||
|
#include "northbridge/intel/i3100/i3100.h"
|
||||||
|
#include "southbridge/intel/i3100/i3100.h"
|
||||||
|
#include <southbridge/intel/i3100/early_smbus.c>
|
||||||
|
|
||||||
|
#define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0)
|
||||||
|
#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
|
||||||
|
|
||||||
|
#define RCBA_RPC 0x0224 /* 32 bit */
|
||||||
|
#define RCBA_HPTC 0x3404 /* 32 bit */
|
||||||
|
#define RCBA_GCS 0x3410 /* 32 bit */
|
||||||
|
#define RCBA_FD 0x3418 /* 32 bit */
|
||||||
|
|
||||||
|
static void early_config(void)
|
||||||
|
{
|
||||||
|
u32 gcs, rpc, fd;
|
||||||
|
|
||||||
|
/* Enable RCBA */
|
||||||
|
pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, DEFAULT_RCBA | 1);
|
||||||
|
|
||||||
|
/* Disable watchdog */
|
||||||
|
gcs = read32(DEFAULT_RCBA + RCBA_GCS);
|
||||||
|
gcs |= (1 << 5); /* No reset */
|
||||||
|
write32(DEFAULT_RCBA + RCBA_GCS, gcs);
|
||||||
|
|
||||||
|
/* Configure PCIe port B as 4x */
|
||||||
|
rpc = read32(DEFAULT_RCBA + RCBA_RPC);
|
||||||
|
rpc |= (3 << 0);
|
||||||
|
write32(DEFAULT_RCBA + RCBA_RPC, rpc);
|
||||||
|
|
||||||
|
/* Disable Modem, Audio, PCIe ports 2/3/4 */
|
||||||
|
fd = read32(DEFAULT_RCBA + RCBA_FD);
|
||||||
|
fd |= (1 << 19) | (1 << 18) | (1 << 17) | (1 << 6) | (1 << 5);
|
||||||
|
write32(DEFAULT_RCBA + RCBA_FD, fd);
|
||||||
|
|
||||||
|
/* Enable HPET */
|
||||||
|
write32(DEFAULT_RCBA + RCBA_HPTC, (1 << 7));
|
||||||
|
|
||||||
|
/* Setup sata mode */
|
||||||
|
pci_write_config8(PCI_DEV(0, 0x1F, 2), SATA_MAP, 0x40);
|
||||||
|
}
|
||||||
|
|
||||||
|
#define DEFAULT_GPIOBASE 0x1180
|
||||||
|
static void setup_gpio(void)
|
||||||
|
{
|
||||||
|
pci_write_config32(PCI_DEV(0, 31, 0), 0x48, DEFAULT_GPIOBASE | 1);
|
||||||
|
pci_write_config8(PCI_DEV(0, 31, 0), 0x4c, (1 << 4));
|
||||||
|
|
||||||
|
outl(0x1b0ce7c0, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */
|
||||||
|
outl(0xec00ffff, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */
|
||||||
|
outl(0xff350000, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
|
||||||
|
outl(0x0000e742, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */
|
||||||
|
outl(0x00000006, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */
|
||||||
|
outl(0x00000300, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */
|
||||||
|
outl(0x00030301, DEFAULT_GPIOBASE + 0x38); /* GPIO_LVL2 */
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
static void i5000_lpc_config(void)
|
||||||
|
{
|
||||||
|
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f);
|
||||||
|
}
|
||||||
|
|
||||||
|
int mainboard_set_fbd_clock(int speed)
|
||||||
|
{
|
||||||
|
switch(speed) {
|
||||||
|
case 533:
|
||||||
|
smbus_write_byte(0x6f, 0x80, 0x21);
|
||||||
|
return 0;
|
||||||
|
case 667:
|
||||||
|
smbus_write_byte(0x6f, 0x80, 0x23);
|
||||||
|
return 0;
|
||||||
|
default:
|
||||||
|
printk(BIOS_ERR, "Invalid clock: %dMHz\n", speed);
|
||||||
|
die("");
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void main(unsigned long bist)
|
||||||
|
{
|
||||||
|
if (bist == 0)
|
||||||
|
enable_lapic();
|
||||||
|
|
||||||
|
i5000_lpc_config();
|
||||||
|
|
||||||
|
w83627hf_enable_serial(PNP_DEV(0x2e, 2), 0x3f8);
|
||||||
|
|
||||||
|
console_init();
|
||||||
|
|
||||||
|
/* Halt if there was a built in self test failure */
|
||||||
|
report_bist_failure(bist);
|
||||||
|
|
||||||
|
early_config();
|
||||||
|
|
||||||
|
setup_gpio();
|
||||||
|
|
||||||
|
enable_smbus();
|
||||||
|
|
||||||
|
/* setup PCIe MMCONF base address */
|
||||||
|
pci_write_config32(PCI_DEV(0, 16, 0), 0x64,
|
||||||
|
CONFIG_MMCONF_BASE_ADDRESS >> 16);
|
||||||
|
|
||||||
|
smbus_write_byte(0x6f, 0x00, 0x63);
|
||||||
|
smbus_write_byte(0x6f, 0x01, 0x04);
|
||||||
|
smbus_write_byte(0x6f, 0x02, 0x53);
|
||||||
|
smbus_write_byte(0x6f, 0x03, 0x39);
|
||||||
|
smbus_write_byte(0x6f, 0x08, 0x06);
|
||||||
|
smbus_write_byte(0x6f, 0x09, 0x00);
|
||||||
|
|
||||||
|
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xf0, DEFAULT_RCBA | 1);
|
||||||
|
i5000_fbdimm_init();
|
||||||
|
smbus_write_byte(0x69, 0x01, 0x01);
|
||||||
|
}
|
||||||
Loading…
Reference in New Issue