From 2d17ea4d501c8e0f68813cda80dd6412b10ca0d8 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Tue, 5 Oct 2021 13:57:30 -0600 Subject: [PATCH] soc/amd/common/block/espi_util: Refactor eSPI Setup eSPI is setup in two different locations in bootblock depending on early port80 routing configuration. Also eSPI is setup in PSP, if verified boot starts before bootblock. Consolidate all the scenarios by initializating eSPI very early in fch_pre_init if verified boot starts after bootblock and eSPI is enabled. BUG=None TEST=Build and boot to OS in Guybrush. Perform S5->S0, G3->S0, warm reset and suspend/resume cycles for 50 iterations each. Signed-off-by: Karthikeyan Ramasubramanian Change-Id: Icfeba17dae0a964c9ca73686e29c18d965589934 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58114 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held Reviewed-by: Raul Rangel --- src/soc/amd/cezanne/bootblock.c | 6 ------ src/soc/amd/cezanne/early_fch.c | 15 +++------------ src/soc/amd/cezanne/include/soc/southbridge.h | 1 - src/soc/amd/common/block/include/amdblocks/espi.h | 11 +++++++++++ src/soc/amd/picasso/early_fch.c | 6 +++--- 5 files changed, 17 insertions(+), 22 deletions(-) diff --git a/src/soc/amd/cezanne/bootblock.c b/src/soc/amd/cezanne/bootblock.c index fc1c5e7c0a..c3cb138473 100644 --- a/src/soc/amd/cezanne/bootblock.c +++ b/src/soc/amd/cezanne/bootblock.c @@ -92,12 +92,6 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp) set_caching(); write_resume_eip(); enable_pci_mmconf(); - /* - * If NO_EARLY_BOOTBLOCK_POSTCODES is selected, we need to initialize port80h - * routing as early as possible - */ - if (CONFIG(NO_EARLY_BOOTBLOCK_POSTCODES)) - configure_port80_routing_early(); /* * base_timestamp is raw tsc value. We need to divide by tsc_freq_mhz diff --git a/src/soc/amd/cezanne/early_fch.c b/src/soc/amd/cezanne/early_fch.c index 7782d43fdd..69458b6220 100644 --- a/src/soc/amd/cezanne/early_fch.c +++ b/src/soc/amd/cezanne/early_fch.c @@ -32,22 +32,16 @@ static void reset_i2c_peripherals(void) sb_reset_i2c_peripherals(&reset_info); } -/* Initialize port80h routing early if needed */ -void configure_port80_routing_early(void) -{ - if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) { - mb_set_up_early_espi(); - espi_setup(); - } -} - /* Before console init */ void fch_pre_init(void) { /* Enable_acpimmio_decode_pm04 to enable the ACPIMMIO decode which is needed to access the GPIO registers. */ enable_acpimmio_decode_pm04(); + /* Setup SPI base by calling lpc_early_init before setting up eSPI. */ lpc_early_init(); + /* Setup eSPI to enable port80 routing. */ + configure_espi(); fch_spi_early_init(); fch_smbus_init(); fch_enable_cf9_io(); @@ -80,7 +74,4 @@ void fch_early_init(void) if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING)) lpc_disable_spi_rom_sharing(); - - if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI) && !CONFIG(NO_EARLY_BOOTBLOCK_POSTCODES)) - espi_setup(); } diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h index 8a1150e0ae..88137075c7 100644 --- a/src/soc/amd/cezanne/include/soc/southbridge.h +++ b/src/soc/amd/cezanne/include/soc/southbridge.h @@ -111,7 +111,6 @@ #define I2C_PAD_CTRL_SPARE0 BIT(17) #define I2C_PAD_CTRL_SPARE1 BIT(18) -void configure_port80_routing_early(void); void fch_pre_init(void); void fch_early_init(void); void fch_init(void *chip_info); diff --git a/src/soc/amd/common/block/include/amdblocks/espi.h b/src/soc/amd/common/block/include/amdblocks/espi.h index 9a563f9e36..7e49ea0f2e 100644 --- a/src/soc/amd/common/block/include/amdblocks/espi.h +++ b/src/soc/amd/common/block/include/amdblocks/espi.h @@ -131,4 +131,15 @@ int espi_setup(void); /* Run mainboard configuration needed to set up eSPI */ void mb_set_up_early_espi(void); +/* Setup eSPI with any mainboard specific initialization. */ +static inline void configure_espi(void) +{ + /* If eSPI is setup in PSP Verstage, continue with that. Else setup eSPI to perform + port80h routing as early as possible. */ + if (!CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) && CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) { + mb_set_up_early_espi(); + espi_setup(); + } +} + #endif /* AMD_BLOCK_ESPI_H */ diff --git a/src/soc/amd/picasso/early_fch.c b/src/soc/amd/picasso/early_fch.c index 3d1cd1b2e7..8771e387bc 100644 --- a/src/soc/amd/picasso/early_fch.c +++ b/src/soc/amd/picasso/early_fch.c @@ -45,7 +45,10 @@ void fch_pre_init(void) /* Enable_acpimmio_decode_pm04 to enable the ACPIMMIO decode which is needed to access the GPIO registers. */ enable_acpimmio_decode_pm04(); + /* Setup SPI base by calling lpc_early_init before setting up eSPI. */ lpc_early_init(); + /* Setup eSPI to enable port80 routing. */ + configure_espi(); if (!CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) lpc_configure_decodes(); @@ -81,7 +84,4 @@ void fch_early_init(void) if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING)) lpc_disable_spi_rom_sharing(); - - if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) - espi_setup(); }