MAINTAINERS: Update RISC-V entry with SiFive and utils
Change-Id: Idd9e51fe2cb7a8497381f5b7440666cd709166b8 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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@ -124,8 +124,11 @@ M: Ronald Minnich <rminnich@gmail.com>
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M: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
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S: Maintained
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F: src/arch/riscv/
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F: src/soc/sifive/
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F: src/soc/ucb/
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F: src/mainboard/emulation/*-riscv/
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F: src/mainboard/sifive/
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F: util/riscv/
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POWER8 ARCHITECTURE
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M: Ronald Minnich <rminnich@gmail.com>
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