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MAINTAINERS: Update RISC-V entry with SiFive and utils 

Change-Id: Idd9e51fe2cb7a8497381f5b7440666cd709166b8
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28757
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Jonathan Neuschäfer 2018-09-25 23:15:16 +02:00 committed by Patrick Georgi
parent 6dff3fdd40
commit 2d1d47bf3e
1 changed files with 3 additions and 0 deletions
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@ -124,8 +124,11 @@ M: Ronald Minnich <rminnich@gmail.com>
M: Jonathan Neuschäfer <j.neuschaefer@gmx.net> M: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
S: Maintained S: Maintained
F: src/arch/riscv/ F: src/arch/riscv/
F: src/soc/sifive/
F: src/soc/ucb/ F: src/soc/ucb/
F: src/mainboard/emulation/*-riscv/ F: src/mainboard/emulation/*-riscv/
F: src/mainboard/sifive/
F: util/riscv/
POWER8 ARCHITECTURE POWER8 ARCHITECTURE
M: Ronald Minnich <rminnich@gmail.com> M: Ronald Minnich <rminnich@gmail.com>