Random fixes for TI pci1x2x / Nokia IP530 / others.
- nokia/ip530/devicetree.cb, southbridge/ti/pci1x2x/pci1x2x.c: - Fix SMSC FDC37B787 name (was a typo). - Disable PS/2 keyboard/mouse LDN, the IP530 doesn't have either. - Fix typo: s/PCI_DEVICE_ID_TI_1420/PCI_DEVICE_ID_TI_1520/. - All of these are confirmed by Marc Bertens on IRC. - Fix a few CHIP_NAME HP board names. - Random whitespace and coding-style fixes. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6212 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann
parent
19d69e3bab
commit
2d1d9cebff
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@ -38,21 +38,28 @@
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/* CONFIG_DEC21143_COMMAND_AND_STATUS_CONFIGURATION try 0x02800107 or 0x02800007 if unsure */
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/**
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* This driver take the values from Kconfig and load them in the registers
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* This driver takes the values from Kconfig and loads them in the registers.
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*/
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static void dec_21143_enable( device_t dev )
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static void dec_21143_enable(device_t dev)
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{
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printk( BIOS_DEBUG, "Init of DECchip 21143 Kconfig style\n");
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// Command and Status Configuration Register (Offset 0x04)
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pci_write_config32( dev, 0x04, CONFIG_DEC21143_COMMAND_AND_STATUS_CONFIGURATION );
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printk( BIOS_DEBUG, "0x04 = %08x (07 01 80 02)\n", pci_read_config32(dev, 0x04) );
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// Cache Line Size Register (Offset 0x0C)
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pci_write_config8( dev, 0x0C, CONFIG_DEC21143_CACHE_LINE_SIZE );
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printk( BIOS_DEBUG, "0x0c = %08x (00 80 00 00)\n", pci_read_config32(dev, 0x0C) );
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// Expansion ROM Base Address Register (Offset 0x30)
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pci_write_config32( dev, 0x30, CONFIG_DEC21143_EXPANSION_ROM_BASE_ADDRESS );
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printk( BIOS_DEBUG, "0x30 = %08x (0x00000000)\n", pci_read_config32(dev, 0x30) );
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return;
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printk(BIOS_DEBUG, "Initializing DECchip 21143\n");
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/* Command and status configuration (offset 0x04) */
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pci_write_config32(dev, 0x04,
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CONFIG_DEC21143_COMMAND_AND_STATUS_CONFIGURATION);
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printk(BIOS_DEBUG, "0x04 = %08x (07 01 80 02)\n",
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pci_read_config32(dev, 0x04));
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/* Cache line size (offset 0x0C) */
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pci_write_config8(dev, 0x0C, CONFIG_DEC21143_CACHE_LINE_SIZE);
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printk(BIOS_DEBUG, "0x0c = %08x (00 80 00 00)\n",
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pci_read_config32(dev, 0x0C));
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/* Expansion ROM base address (offset 0x30) */
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pci_write_config32(dev, 0x30,
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CONFIG_DEC21143_EXPANSION_ROM_BASE_ADDRESS);
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printk(BIOS_DEBUG, "0x30 = %08x (0x00000000)\n",
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pci_read_config32(dev, 0x30));
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}
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static struct device_operations dec_21143_ops = {
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@ -25,5 +25,5 @@
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#include "chip.h"
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struct chip_operations mainboard_ops = {
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CHIP_NAME("HP DL145G1 Mainboard")
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CHIP_NAME("HP ProLiant DL145 G1 Mainboard")
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};
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@ -30,5 +30,5 @@
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#include "chip.h"
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struct chip_operations mainboard_ops = {
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CHIP_NAME("HP DL145 G3 Mainboard")
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CHIP_NAME("HP ProLiant DL145 G3 Mainboard")
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};
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@ -30,5 +30,5 @@
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#include "chip.h"
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struct chip_operations mainboard_ops = {
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CHIP_NAME("HP DL165 G6 Mainboard (Family 10)")
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CHIP_NAME("HP ProLiant DL165 G6 Mainboard (Fam10h)")
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};
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@ -19,9 +19,9 @@
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##
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chip northbridge/intel/i440bx # Northbridge
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device lapic_cluster 0 on # APIC cluster
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chip cpu/intel/socket_PGA370 # CPU
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device lapic 0 on end # APIC
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device lapic_cluster 0 on # (L)APIC cluster
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chip cpu/intel/socket_PGA370 # CPU socket
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device lapic 0 on end # Local APIC of the CPU
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end
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end
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device pci_domain 0 on # PCI domain
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@ -29,7 +29,7 @@ chip northbridge/intel/i440bx # Northbridge
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device pci 1.0 on end # PCI/AGP bridge
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chip southbridge/intel/i82371eb # Southbridge
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device pci 7.0 on # ISA bridge
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chip superio/smsc/smscsuperio # Super I/O (SMSC FDC37C878)
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chip superio/smsc/smscsuperio # Super I/O (SMSC FDC37B787)
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device pnp 3f0.0 off end # Floppy (No connector)
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device pnp 3f0.3 off end # Parallel port (No connector)
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device pnp 3f0.4 on # COM1
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@ -40,10 +40,10 @@ chip northbridge/intel/i440bx # Northbridge
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 3f0.7 on end # PS/2 keyboard / mouse
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device pnp 3f0.6 on end # RTC
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device pnp 3f0.7 off end # PS/2 keyboard / mouse (No connector)
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device pnp 3f0.8 on end # AUX I/O
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device pnp 3f0.A off end # ACPI (No support yet)
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device pnp 3f0.a off end # ACPI (No support yet)
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end
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end
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device pci 7.1 on end # IDE
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@ -24,38 +24,40 @@
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#include <device/pci_ops.h>
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#include <console/console.h>
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#if ( !defined( CONFIG_TI_PCMCIA_CARDBUS_CMDR ) || \
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!defined( CONFIG_TI_PCMCIA_CARDBUS_CLSR ) || \
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!defined( CONFIG_TI_PCMCIA_CARDBUS_CLTR ) || \
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!defined( CONFIG_TI_PCMCIA_CARDBUS_BCR ) || \
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!defined( CONFIG_TI_PCMCIA_CARDBUS_SCR ) || \
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!defined( CONFIG_TI_PCMCIA_CARDBUS_MRR ) )
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#if (!defined(CONFIG_TI_PCMCIA_CARDBUS_CMDR) || \
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!defined(CONFIG_TI_PCMCIA_CARDBUS_CLSR) || \
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!defined(CONFIG_TI_PCMCIA_CARDBUS_CLTR) || \
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!defined(CONFIG_TI_PCMCIA_CARDBUS_BCR) || \
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!defined(CONFIG_TI_PCMCIA_CARDBUS_SCR) || \
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!defined(CONFIG_TI_PCMCIA_CARDBUS_MRR))
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#error "you must supply these values in your mainboard-specific Kconfig file"
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#endif
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static void ti_pci1x2y_init(struct device *dev)
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{
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printk(BIOS_INFO, "Init of Texas Instruments PCI1x2x PCMCIA/CardBus controller\n");
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// Command register (offset 04)
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pci_write_config16( dev, 0x04, CONFIG_TI_PCMCIA_CARDBUS_CMDR );
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// Cache Line Size Register (offset 0x0C)
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pci_write_config8( dev, 0x0C, CONFIG_TI_PCMCIA_CARDBUS_CLSR );
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// CardBus latency timer register (offset 1B)
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pci_write_config8( dev, 0x1B, CONFIG_TI_PCMCIA_CARDBUS_CLTR );
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// Bridge control register (offset 3E)
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pci_write_config16( dev, 0x3E, CONFIG_TI_PCMCIA_CARDBUS_BCR );
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/** Enable change sub-vendor id
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* Clear the bit 5 to enable to write to the sub-vendor/device ids at 40 and 42 */
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pci_write_config32( dev, 0x80, 0x10 );
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pci_write_config32( dev, 0x40, PCI_VENDOR_ID_NOKIA );
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// Now write the correct value for SCR
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// System Control Register (offset 0x80)
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pci_write_config32( dev, 0x80, CONFIG_TI_PCMCIA_CARDBUS_SCR );
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// Multifunction routing register
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pci_write_config32( dev, 0x8C, CONFIG_TI_PCMCIA_CARDBUS_MRR );
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// Set Device Control Register (0x92) accordingly
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pci_write_config8( dev, 0x92, pci_read_config8( dev, 0x92 ) | 0x02 );
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return;
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/* Command (offset 04) */
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pci_write_config16(dev, 0x04, CONFIG_TI_PCMCIA_CARDBUS_CMDR);
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/* Cache Line Size (offset 0x0C) */
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pci_write_config8(dev, 0x0C, CONFIG_TI_PCMCIA_CARDBUS_CLSR);
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/* CardBus latency timer (offset 0x1B) */
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pci_write_config8(dev, 0x1B, CONFIG_TI_PCMCIA_CARDBUS_CLTR);
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/* Bridge control (offset 0x3E) */
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pci_write_config16(dev, 0x3E, CONFIG_TI_PCMCIA_CARDBUS_BCR);
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/*
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* Enable change sub-vendor ID. Clear the bit 5 to enable to write
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* to the sub-vendor/device ids at 40 and 42.
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*/
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pci_write_config32(dev, 0x80, 0x10);
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pci_write_config32(dev, 0x40, PCI_VENDOR_ID_NOKIA);
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/* Now write the correct value for SCR. */
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/* System control (offset 0x80) */
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pci_write_config32(dev, 0x80, CONFIG_TI_PCMCIA_CARDBUS_SCR);
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/* Multifunction routing */
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pci_write_config32(dev, 0x8C, CONFIG_TI_PCMCIA_CARDBUS_MRR);
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/* Set the device control register (0x92) accordingly. */
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pci_write_config8(dev, 0x92, pci_read_config8(dev, 0x92) | 0x02);
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}
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static struct device_operations ti_pci1x2y_ops = {
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@ -81,5 +83,5 @@ static const struct pci_driver ti_pci1420_driver __pci_driver = {
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static const struct pci_driver ti_pci1520_driver __pci_driver = {
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.ops = &ti_pci1x2y_ops,
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.vendor = PCI_VENDOR_ID_TI,
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.device = PCI_DEVICE_ID_TI_1420,
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.device = PCI_DEVICE_ID_TI_1520,
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};
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