soc/intel/common: Move update_mrc_cache after BS_DEV_ENUMERATE
This patch ensures that MRC cache data is already written into SPI chip before SPI protected regions are getting locked during BS_DEV_RESOURCES-BS_ON_EXIT. This requirements are intended to support platform security guideline where all required chipset registers are expected to be in lock down stage before launching any 3rd party code as in option rom etc. coreboot has to change its execution order to meet those requirements. Hence storing mrc cache data into SPI has been moved right after pci enumeration is done, so that SPI registers can be lock down before calling post pci enumeration FSP NotifyPhase() API which is targeted to be done in BS_DEV_ENABLE-BS_ON_ENTRY. TEST=Ensure MRC training data is stored into SPI chip and power_ Resume autotest is passing. Change-Id: I8ee26b5cc70433438cf4e45e707b8a54f89cf9b0 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21028 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -531,4 +531,9 @@ static void update_mrc_cache(void *unused)
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protect_mrc_region();
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}
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BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL);
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/*
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* Ensures MRC training data is stored into SPI after PCI enumeration is done
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* during BS_DEV_ENUMERATE-BS_ON_EXIT and lock down SPI protected ranges
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* during BS_DEV_RESOURCES-BS_ON_EXIT.
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*/
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BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_EXIT, update_mrc_cache, NULL);
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