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mb/google/brya/var/kano: Correct SSD power sequence 

M.2 spec describes PERST# should be sequenced after power enable.

BUG=b:192137970
TEST=FW_NAME=kano emerge-brya coreboot and boot to OS.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I20bf5ca66c6d05229c6d72058c5a73f38a58be3d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
David Wu 2021-10-12 13:19:35 +08:00 committed by Tim Wawrzynczak
parent d0975ff5d5
commit 2d2cc0dcb9
2 changed files with 17 additions and 0 deletions
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2
src/mainboard/google/brya/variants/kano/Makefile.inc
View File

@ -1,6 +1,8 @@
# SPDX-License-Identifier: GPL-2.0-only
bootblock-y += gpio.c
romstage-y += gpio.c
ramstage-y += gpio.c
ramstage-$(CONFIG_FW_CONFIG) += fw_config.c

15
src/mainboard/google/brya/variants/kano/gpio.c
View File

@ -103,6 +103,8 @@ static const struct pad_config override_gpio_table[] = {
static const struct pad_config early_gpio_table[] = {
/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
/* B4 : PROC_GP3 ==> SSD_PERST_L */
PAD_CFG_GPO(GPP_B4, 0, DEEP),
/* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
/* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
@ -118,6 +120,8 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_GPO(GPP_D1, 0, DEEP),
/* D2 : ISH_GP2 ==> EN_FP_PWR */
PAD_CFG_GPO(GPP_D2, 1, DEEP),
/* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
PAD_CFG_GPO(GPP_D11, 1, DEEP),
/* E0 : SATAXPCIE0 ==> NC */
PAD_NC(GPP_E0, NONE),
/* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
@ -154,6 +158,11 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, DEEP, NF1),
};
static const struct pad_config romstage_gpio_table[] = {
/* B4 : PROC_GP3 ==> SSD_PERST_L */
PAD_CFG_GPO(GPP_B4, 1, DEEP),
};
const struct pad_config *variant_gpio_override_table(size_t *num)
{
*num = ARRAY_SIZE(override_gpio_table);
@ -165,3 +174,9 @@ const struct pad_config *variant_early_gpio_table(size_t *num)
*num = ARRAY_SIZE(early_gpio_table);
return early_gpio_table;
}
const struct pad_config *variant_romstage_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(romstage_gpio_table);
return romstage_gpio_table;
}