mb/google/hatch: Enable NVME support for Hatch

This patch enables the x4 NVME device for hatch,
* Enable the Root port 9.
* Assign the usage type for clock source.
* Configure the GPIO for CLK SRC 1.

BUG=b:120914069
BRANCH=none
TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot.

Change-Id: I69be6b21a5ae5962877a5c38180b5ffac532fed4
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/30431
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/hatch/variants/baseboard/devicetree.cb

@@ -63,6 +63,13 @@ chip soc/intel/cannonlake
 	register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# WWAN
 	register "usb3_ports[5]" = "USB3_PORT_EMPTY"
 
+	# Enable Root port 9(x4) for NVMe.
+	register "PcieRpEnable[8]" = "1"
+	# RP 9 uses CLK SRC 1
+	register "PcieClkSrcUsage[1]" = "8"
+	# ClkReq-to-ClkSrc mapping for CLK SRC 1
+	register "PcieClkSrcClkReq[1]" = "1"
+
 	device domain 0 on
 		device pci 00.0 on end # Host Bridge
 		device pci 02.0 on  end # Integrated Graphics Device
@@ -178,7 +185,7 @@ chip soc/intel/cannonlake
 		device pci 1c.5 off end # PCI Express Port 6
 		device pci 1c.6 off end # PCI Express Port 7
 		device pci 1c.7 off end # PCI Express Port 8
-		device pci 1d.0 off end # PCI Express Port 9
+		device pci 1d.0 on  end # PCI Express Port 9 (X4 NVME)
 		device pci 1d.1 off end # PCI Express Port 10
 		device pci 1d.2 off end # PCI Express Port 11
 		device pci 1d.3 off end # PCI Express Port 12

src/mainboard/google/hatch/variants/baseboard/gpio.c

@@ -21,6 +21,8 @@
 static const struct pad_config gpio_table[] = {
 	/* TRACKPAD_INT_ODL */
 	PAD_CFG_GPI_APIC(GPP_A21, NONE, PLTRST, LEVEL, INVERT),
+	/* SRCCLKREQ1 */
+	PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
 	/* H1_SLAVE_SPI_CS_L */
 	PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
 	/* H1_SLAVE_SPI_CLK */