mb/asus/kgpe-d16: Enable TPM when selected in Kconfig

Issue TPM startup on romstage completion via common LPC TPM
code if the TPM was enabled in Kconfig.

Change-Id: Id886d6aeefa045fb979f128b1cf4c10fff243b24
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://review.coreboot.org/19338
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Timothy Pearson 2017-04-17 12:16:43 -05:00
parent 992c7dba7e
commit 2d35809530
1 changed files with 5 additions and 1 deletions

View File

@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015 - 2016 Raptor Engineering, LLC
* Copyright (C) 2015 - 2017 Raptor Engineering, LLC
*
* Copyright (C) 2007 AMD
* Written by Yinghai Lu <yinghailu@amd.com> for AMD.
@ -45,6 +45,7 @@
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
#include <arch/early_variables.h>
#include <cbmem.h>
#include <tpm.h>
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
@ -622,6 +623,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
pci_write_config16(PCI_DEV(0, 0x14, 0), 0x56, 0x0bb0);
pci_write_config16(PCI_DEV(0, 0x14, 0), 0x5a, 0x0ff0);
if (IS_ENABLED(CONFIG_LPC_TPM))
init_tpm(s3resume);
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
}