cpu,soc/x86: always include cpu/x86/mtrr on x86 CPUs/SoCs

All x86-based CPUs and SoCs in the coreboot tree end up including the
Makefile in cpu/x86/mtrr, so include this directly in the Makefile in
cpu/x86 to add it for all x86 CPUs/SoCs. In the unlikely case that a new
x86 CPU/SoC will be added, a CPU_X86_MTRR Kconfig option that is
selected be default could be added and the new CPU/SoC without MTRR
support can override this option that then will be used in the Makefile
to guard adding the Makefile from the cpu/x86/mtrr sub-directory.

In cpu/intel all models except model 2065X and 206AX are selcted by a
socket and rely on the socket's Makefile.inc to add x86/mtrr to the
subdirs, so those models don't add x86/mtrr themselves. The Intel
Broadwell SoC selects CPU_INTEL_HASWELL and which added x86/mtrr to the
subdirs. The Intel Xeon SP SoC directory contains two sub-folders for
different versions or generations which both add x86/mtrr to the subdirs
in their Makefiles.

Change-Id: I743eaac99a85a5c712241ba48a320243c5a51f76
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

src/cpu/amd/agesa/family14/Makefile.inc

@@ -9,5 +9,4 @@ ramstage-y += model_14_init.c
 subdirs-y += ../../mtrr
 subdirs-y += ../../../x86/lapic
 subdirs-y += ../../../x86/cache
-subdirs-y += ../../../x86/mtrr
 subdirs-y += ../../../x86/pae

src/cpu/amd/agesa/family15tn/Makefile.inc

@@ -12,5 +12,4 @@ subdirs-y += ../../mtrr
 subdirs-y += ../../smm
 subdirs-y += ../../../x86/lapic
 subdirs-y += ../../../x86/cache
-subdirs-y += ../../../x86/mtrr
 subdirs-y += ../../../x86/pae

src/cpu/amd/agesa/family16kb/Makefile.inc

@@ -9,5 +9,4 @@ ramstage-y += model_16_init.c
 subdirs-y += ../../mtrr
 subdirs-y += ../../../x86/lapic
 subdirs-y += ../../../x86/cache
-subdirs-y += ../../../x86/mtrr
 subdirs-y += ../../../x86/pae

src/cpu/amd/pi/00730F01/Makefile.inc

@@ -10,5 +10,4 @@ ramstage-y += update_microcode.c
 subdirs-y += ../../mtrr
 subdirs-y += ../../../x86/lapic
 subdirs-y += ../../../x86/cache
-subdirs-y += ../../../x86/mtrr
 subdirs-y += ../../../x86/pae

src/cpu/intel/haswell/Makefile.inc

@@ -15,7 +15,6 @@ bootblock-y += bootblock.c
 
 postcar-y += ../car/non-evict/exit_car.S
 
-subdirs-y += ../../x86/mtrr
 subdirs-y += ../../x86/lapic
 subdirs-y += ../../x86/cache
 subdirs-y += ../microcode

src/cpu/intel/model_2065x/Makefile.inc

@@ -1,7 +1,6 @@
 ramstage-y += model_2065x_init.c
 subdirs-y += ../../x86/name
 subdirs-y += ../../x86/cache
-subdirs-y += ../../x86/mtrr
 subdirs-y += ../../x86/lapic
 subdirs-y += ../../intel/turbo
 subdirs-y += ../../intel/microcode

src/cpu/intel/model_206ax/Makefile.inc

@@ -2,7 +2,6 @@ ramstage-y += model_206ax_init.c
 subdirs-y += ../../x86/name
 subdirs-y += ../smm/gen1
 
-subdirs-y += ../../x86/mtrr
 subdirs-y += ../../x86/lapic
 subdirs-y += ../../x86/cache
 subdirs-y += ../microcode

src/cpu/intel/slot_1/Makefile.inc

@@ -7,7 +7,6 @@ subdirs-y += ../model_65x
 subdirs-y += ../model_67x
 subdirs-y += ../model_68x
 subdirs-y += ../model_6bx
-subdirs-y += ../../x86/mtrr
 subdirs-y += ../../x86/lapic
 subdirs-y += ../../x86/cache
 subdirs-y += ../microcode

src/cpu/intel/socket_441/Makefile.inc

@@ -1,5 +1,4 @@
 subdirs-y += ../model_106cx
-subdirs-y += ../../x86/mtrr
 subdirs-y += ../../x86/lapic
 subdirs-y += ../../x86/cache
 subdirs-y += ../microcode

src/cpu/intel/socket_BGA956/Makefile.inc

@@ -1,5 +1,4 @@
 subdirs-y += ../model_1067x
-subdirs-y += ../../x86/mtrr
 subdirs-y += ../../x86/lapic
 subdirs-y += ../../x86/cache
 subdirs-y += ../microcode

src/cpu/intel/socket_FCBGA559/Makefile.inc

@@ -1,5 +1,4 @@
 subdirs-y += ../model_106cx
-subdirs-y += ../../x86/mtrr
 subdirs-y += ../../x86/lapic
 subdirs-y += ../../x86/cache
 subdirs-y += ../microcode

src/cpu/intel/socket_LGA775/Makefile.inc

@@ -4,7 +4,6 @@ subdirs-y += ../model_f4x
 #subdirs-y += ../model_f6x
 #subdirs-y += ../model_1066x
 subdirs-y += ../model_1067x
-subdirs-y += ../../x86/mtrr
 subdirs-y += ../../x86/lapic
 subdirs-y += ../../x86/cache
 subdirs-y += ../microcode

src/cpu/intel/socket_m/Makefile.inc

@@ -1,6 +1,5 @@
 subdirs-y += ../model_6ex
 subdirs-y += ../model_6fx
-subdirs-y += ../../x86/mtrr
 subdirs-y += ../../x86/lapic
 subdirs-y += ../../x86/cache
 subdirs-y += ../microcode

src/cpu/intel/socket_mPGA604/Makefile.inc

@@ -1,5 +1,4 @@
 subdirs-y += ../model_f2x
-subdirs-y += ../../x86/mtrr
 subdirs-y += ../../x86/lapic
 subdirs-y += ../../x86/cache
 subdirs-y += ../microcode

src/cpu/intel/socket_p/Makefile.inc

@@ -1,6 +1,5 @@
 subdirs-y += ../model_6fx
 subdirs-y += ../model_1067x
-subdirs-y += ../../x86/mtrr
 subdirs-y += ../../x86/lapic
 subdirs-y += ../../x86/cache
 subdirs-y += ../microcode

src/cpu/qemu-x86/Makefile.inc

@@ -7,5 +7,4 @@ romstage-y += ../intel/car/romstage.c
 
 ramstage-y += qemu.c
 
-subdirs-y += ../x86/mtrr
 subdirs-y += ../x86/lapic

src/cpu/x86/Makefile.inc

@@ -1,3 +1,4 @@
+subdirs-y += mtrr
 subdirs-y += pae
 subdirs-$(CONFIG_HAVE_SMI_HANDLER) += smm
 subdirs-$(CONFIG_UDELAY_TSC) += tsc

src/soc/amd/cezanne/Makefile.inc

@@ -3,7 +3,6 @@
 ifeq ($(CONFIG_SOC_AMD_CEZANNE),y)
 
 subdirs-y += ../../../cpu/x86/lapic
-subdirs-y += ../../../cpu/x86/mtrr
 
 subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage
 

src/soc/amd/picasso/Makefile.inc

@@ -4,7 +4,6 @@ ifeq ($(CONFIG_SOC_AMD_PICASSO),y)
 
 subdirs-y += ../../../cpu/x86/lapic
 subdirs-y += ../../../cpu/x86/cache
-subdirs-y += ../../../cpu/x86/mtrr
 subdirs-y += ../../../cpu/x86/pae
 subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage
 subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += ../common/psp_verstage

src/soc/amd/stoneyridge/Makefile.inc

@@ -5,7 +5,6 @@ ifeq ($(CONFIG_SOC_AMD_STONEYRIDGE),y)
 subdirs-y += ../../../cpu/amd/mtrr/
 subdirs-y += ../../../cpu/x86/lapic
 subdirs-y += ../../../cpu/x86/cache
-subdirs-y += ../../../cpu/x86/mtrr
 subdirs-y += ../../../cpu/x86/pae
 
 bootblock-y += uart.c

src/soc/example/min86/Makefile.inc

@@ -10,6 +10,4 @@ romstage-y	+= romstage.c
 ramstage-y	+= chip.c
 ramstage-y	+= timer.c
 
-subdirs-y	+= ../../../cpu/x86/mtrr
-
 endif

src/soc/intel/alderlake/Makefile.inc

@@ -3,7 +3,6 @@ subdirs-y += romstage
 subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/intel/turbo
 subdirs-y += ../../../cpu/x86/lapic
-subdirs-y += ../../../cpu/x86/mtrr
 
 # all (bootblock, verstage, romstage, postcar, ramstage)
 all-y += gspi.c

src/soc/intel/apollolake/Makefile.inc

@@ -4,7 +4,6 @@ subdirs-y += ../../../cpu/intel/common
 subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/intel/turbo
 subdirs-y += ../../../cpu/x86/lapic
-subdirs-y += ../../../cpu/x86/mtrr
 subdirs-y += ../../../cpu/x86/cache
 
 bootblock-y += bootblock/bootblock.c

src/soc/intel/baytrail/Makefile.inc

@@ -2,7 +2,6 @@ ifeq ($(CONFIG_SOC_INTEL_BAYTRAIL),y)
 
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
-subdirs-y += ../../../cpu/x86/mtrr
 subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/intel/turbo
 subdirs-y += ../../../cpu/intel/common

src/soc/intel/braswell/Makefile.inc

@@ -2,7 +2,6 @@ ifeq ($(CONFIG_SOC_INTEL_BRASWELL),y)
 
 subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/lapic
-subdirs-y += ../../../cpu/x86/mtrr
 subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/intel/turbo
 subdirs-y += ../../../cpu/intel/common

src/soc/intel/cannonlake/Makefile.inc

@@ -4,7 +4,6 @@ subdirs-y += romstage
 subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/intel/turbo
 subdirs-y += ../../../cpu/x86/lapic
-subdirs-y += ../../../cpu/x86/mtrr
 subdirs-y += ../../../cpu/intel/common
 
 bootblock-y += bootblock/bootblock.c

src/soc/intel/denverton_ns/Makefile.inc

@@ -5,7 +5,6 @@ ifeq ($(CONFIG_SOC_INTEL_DENVERTON_NS),y)
 subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/intel/turbo
 subdirs-y += ../../../cpu/x86/lapic
-subdirs-y += ../../../cpu/x86/mtrr
 subdirs-y += ../../../cpu/x86/cache
 
 bootblock-y += bootblock/bootblock.c

src/soc/intel/elkhartlake/Makefile.inc

@@ -4,7 +4,6 @@ subdirs-y += romstage
 subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/intel/turbo
 subdirs-y += ../../../cpu/x86/lapic
-subdirs-y += ../../../cpu/x86/mtrr
 
 # all (bootblock, verstage, romstage, postcar, ramstage)
 all-y += gspi.c

src/soc/intel/icelake/Makefile.inc

@@ -4,7 +4,6 @@ subdirs-y += romstage
 subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/intel/turbo
 subdirs-y += ../../../cpu/x86/lapic
-subdirs-y += ../../../cpu/x86/mtrr
 
 # all (bootblock, verstage, romstage, postcar, ramstage)
 all-y += gspi.c

src/soc/intel/jasperlake/Makefile.inc

@@ -4,7 +4,6 @@ subdirs-y += romstage
 subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/intel/turbo
 subdirs-y += ../../../cpu/x86/lapic
-subdirs-y += ../../../cpu/x86/mtrr
 
 # all (bootblock, verstage, romstage, postcar, ramstage)
 all-y += gspi.c

src/soc/intel/quark/Makefile.inc

@@ -3,7 +3,6 @@
 ifeq ($(CONFIG_SOC_INTEL_QUARK),y)
 
 subdirs-y += romstage
-subdirs-y += ../../../cpu/x86/mtrr
 
 bootblock-y += bootblock/esram_init.S
 bootblock-y += bootblock/bootblock.c

src/soc/intel/skylake/Makefile.inc

@@ -6,7 +6,6 @@ subdirs-y += ../../../cpu/intel/common
 subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/intel/turbo
 subdirs-y += ../../../cpu/x86/lapic
-subdirs-y += ../../../cpu/x86/mtrr
 
 bootblock-y += bootblock/bootblock.c
 bootblock-y += i2c.c

src/soc/intel/tigerlake/Makefile.inc

@@ -4,7 +4,6 @@ subdirs-y += romstage
 subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/intel/turbo
 subdirs-y += ../../../cpu/x86/lapic
-subdirs-y += ../../../cpu/x86/mtrr
 
 # all (bootblock, verstage, romstage, postcar, ramstage)
 all-y += gspi.c

src/soc/intel/xeon_sp/cpx/Makefile.inc

@@ -4,7 +4,6 @@ ifeq ($(CONFIG_SOC_INTEL_COOPERLAKE_SP),y)
 
 subdirs-y += ../../../../cpu/intel/turbo
 subdirs-y += ../../../../cpu/x86/lapic
-subdirs-y += ../../../../cpu/x86/mtrr
 subdirs-y += ../../../../cpu/intel/microcode
 
 romstage-y += romstage.c ddr.c

src/soc/intel/xeon_sp/skx/Makefile.inc

@@ -5,7 +5,6 @@ ifeq ($(CONFIG_SOC_INTEL_SKYLAKE_SP),y)
 subdirs-y += ../../../../cpu/intel/microcode
 subdirs-y += ../../../../cpu/intel/turbo
 subdirs-y += ../../../../cpu/x86/lapic
-subdirs-y += ../../../../cpu/x86/mtrr
 subdirs-y += ../../../../cpu/x86/cache
 
 postcar-y += soc_util.c