src: Drop unused include <timestamp.h>

Change-Id: I7e181111cd1b837382929071a350b94c3afc1aaa
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This commit is contained in:
Elyes HAOUAS 2019-03-06 13:06:54 +01:00 committed by Patrick Georgi
parent ae546422ed
commit 2d4e836f11
28 changed files with 0 additions and 29 deletions

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@ -15,7 +15,6 @@
#include <fsp/util.h>
#include <memrange.h>
#include <string.h>
#include <timestamp.h>
#include <cbfs.h>
void fsp_temp_ram_exit(void)

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@ -23,7 +23,6 @@
#include <string.h>
#include <cbfs.h>
#include <program_loading.h>
#include <timestamp.h>
#include <memrange.h>
#include <fit.h>
#include <boardid.h>

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@ -13,7 +13,6 @@
#include <console/console.h>
#include <string.h>
#include <lib.h>
#include <timestamp.h>
#include "lzmadecode.h"

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@ -16,7 +16,6 @@
#include <stdint.h>
#include <string.h>
#include <timestamp.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <cpu/x86/lapic.h>

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@ -14,7 +14,6 @@
*/
#include <bootblock_common.h>
#include <timestamp.h>
#include "board.h"
void bootblock_mainboard_init(void)

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@ -16,7 +16,6 @@
#include <device/device.h>
#include <bootblock_common.h>
#include <gpio.h>
#include <timestamp.h>
static void setup_usb(void)
{

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@ -16,7 +16,6 @@
#include <stdint.h>
#include <string.h>
#include <timestamp.h>
#include <device/pci_ops.h>
#include <device/pci.h>
#include <device/pci_def.h>

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@ -16,7 +16,6 @@
#include <stdint.h>
#include <string.h>
#include <timestamp.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <cpu/x86/lapic.h>

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@ -16,7 +16,6 @@
#include <stdint.h>
#include <string.h>
#include <timestamp.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <cpu/x86/lapic.h>

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@ -18,7 +18,6 @@
#include <arch/cbfs.h>
#include <cpu/x86/mtrr.h>
#include <romstage_handoff.h>
#include <timestamp.h>
#include <soc/gpio.h>
#include <soc/iomap.h>
#include <soc/lpc.h>

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@ -16,7 +16,6 @@
#include <stdint.h>
#include <string.h>
#include <timestamp.h>
#include <arch/io.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>

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@ -28,8 +28,6 @@
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
#include <superio/winbond/common/winbond.h>
#include <timestamp.h>
void pch_enable_lpc(void)
{

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@ -18,7 +18,6 @@
#include <stdint.h>
#include <string.h>
#include <timestamp.h>
#include <arch/byteorder.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>

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@ -17,7 +17,6 @@
#include <stdint.h>
#include <string.h>
#include <timestamp.h>
#include <arch/byteorder.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>

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@ -17,7 +17,6 @@
#include <stdint.h>
#include <string.h>
#include <timestamp.h>
#include <arch/byteorder.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>

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@ -16,7 +16,6 @@
#include <stdint.h>
#include <string.h>
#include <timestamp.h>
#include <arch/io.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>

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@ -16,7 +16,6 @@
#include <stdint.h>
#include <string.h>
#include <timestamp.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <cpu/x86/lapic.h>

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@ -19,7 +19,6 @@
#include <console/console.h>
#include <cpu/x86/mtrr.h>
#include <romstage_handoff.h>
#include <timestamp.h>
#include <soc/gpio.h>
#include <soc/iomap.h>
#include <soc/lpc.h>

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@ -31,7 +31,6 @@
#include <console/vtxprintf.h>
#include <fmap.h>
#include <stdlib.h>
#include <timestamp.h>
#include <vboot_struct.h>
#include <security/vboot/vbnv.h>
#include <security/vboot/misc.h>

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@ -18,7 +18,6 @@
#include <soc/cpu.h>
#include <stdint.h>
#include <timer.h>
#include <timestamp.h>
#define PISTACHIO_CLOCK_SWITCH 0xB8144200
#define MIPS_EXTERN_PLL_BYPASS_MASK 0x00000002

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@ -37,7 +37,6 @@
#include <stage_cache.h>
#include <stddef.h>
#include <stdint.h>
#include <timestamp.h>
#include <vendorcode/google/chromeos/chromeos.h>
/* SOC initialization before RAM is enabled */

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@ -26,7 +26,6 @@
#include <soc/nvidia/tegra/apbmisc.h>
#include <soc/pmc.h>
#include <soc/power.h>
#include <timestamp.h>
#define BCT_OFFSET_IN_BIT 0x4c
#define ODMDATA_OFFSET_IN_BCT 0x508

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@ -29,7 +29,6 @@
#include <soc/nvidia/tegra/apbmisc.h>
#include <symbols.h>
#include <timer.h>
#include <timestamp.h>
#include <vendorcode/google/chromeos/chromeos.h>
void __weak romstage_mainboard_init(void)

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@ -20,7 +20,6 @@
#include <console/console.h>
#include <string.h>
#include <timer.h>
#include <timestamp.h>
#include <program_loading.h>
#include <soc/iomap.h>

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@ -18,7 +18,6 @@
#include <console/console.h>
#include <delay.h>
#include <timer.h>
#include <timestamp.h>
#include <commonlib/helpers.h>
#include <assert.h>

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@ -17,7 +17,6 @@
#include <types.h>
#include <delay.h>
#include <timer.h>
#include <timestamp.h>
#include <gpio.h>

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@ -15,7 +15,6 @@
#include <symbols.h>
#include <device/device.h>
#include <timestamp.h>
#include <soc/mmu.h>
#include <soc/symbols.h>

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@ -20,7 +20,6 @@
#include <soc/grf.h>
#include <soc/timer.h>
#include <symbols.h>
#include <timestamp.h>
void bootblock_soc_init(void)
{