soc/intel/jasperlake: Disable multiphase SI init
Jasper Lake does not have any use case for multiphase SI init so Disable it. BUG=b:162184827 BRANCH=None TEST=Build and boot JSLRVP Cq-Depend: chrome-internal:3221772 Change-Id: I2d591b46c403e68ff0b41ac8f87c742ae774111e Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
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@ -349,6 +349,12 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
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mainboard_silicon_init_params(params);
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}
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/* Disable Multiphase Si init */
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int soc_fsp_multi_phase_init_is_enable(void)
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{
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return 0;
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}
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/* Mainboard GPIO Configuration */
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__weak void mainboard_silicon_init_params(FSP_S_CONFIG *params)
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{
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