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mb/google/octopus: Configure H1 interrupt pad using Rx level config 

This change configures GPIO_63 (which is used for H1 interrupts) as Rx
Level. This ensures that the signal gets passed on to the next logic
state as is and the APIC entry can be configured to trigger interrupt
on level or edge as per the kernel driver expectation.

TEST=Verified that no H1 interrupt timeouts are seen with 100
iterations of warm and 100 iterations of cold reboot.

Change-Id: I7aac30300a4251d9b40276dcca7ebc6a6d814c40
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Furquan Shaikh 2018-09-05 13:59:00 -07:00
parent 401f8c59bd
commit 2d602098f9
6 changed files with 8 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/mainboard/google/octopus/variants/baseboard/gpio.c
View File

@ -91,7 +91,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_60, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_RXD */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_61, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_TXD */
PAD_NC(GPIO_62, UP_20K), /* UART0-RTS_B -- unused */
PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE, DISPUPD), /* H1_PCH_INT_ODL */
PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD), /* H1_PCH_INT_ODL */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART2_RXD */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* LPSS_UART2_TXD */
PAD_NC(GPIO_66, UP_20K), /* UART2-RTS_B -- unused */
@ -297,7 +297,7 @@ const struct pad_config *__weak variant_override_gpio_table(size_t *num)
static const struct pad_config early_gpio_table[] = {
PAD_CFG_GPI(GPIO_190, NONE, DEEP), /* PCH_WP_OD */
/* GSPI0_INT */
PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE,
PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, LEVEL, INVERT, TxDRxE,
DISPUPD), /* H1_PCH_INT_ODL */
/* GSPI0_CLK */
PAD_CFG_NF(GPIO_79, NONE, DEEP, NF1), /* H1_SLAVE_SPI_CLK_R */

4
src/mainboard/google/octopus/variants/bip/gpio.c
View File

@ -89,7 +89,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_60, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_RXD */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_61, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_TXD */
PAD_NC(GPIO_62, UP_20K), /* UART0-RTS_B -- unused */
PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE, DISPUPD), /* H1_PCH_INT_ODL */
PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD), /* H1_PCH_INT_ODL */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART2_RXD */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* LPSS_UART2_TXD */
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_66, 1, DEEP, UP_20K, HIZCRx0, DISPUPD), /* UART2-RTS_B -- LTE_OFF_ODL*/
@ -290,7 +290,7 @@ const struct pad_config *variant_base_gpio_table(size_t *num)
static const struct pad_config early_gpio_table[] = {
PAD_CFG_GPI(GPIO_190, NONE, DEEP), /* PCH_WP_OD */
/* GSPI0_INT */
PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE,
PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, LEVEL, INVERT, TxDRxE,
DISPUPD), /* H1_PCH_INT_ODL */
/* GSPI0_CLK */
PAD_CFG_NF(GPIO_79, NONE, DEEP, NF1), /* H1_SLAVE_SPI_CLK_R */

2
src/mainboard/google/octopus/variants/bobba/gpio.c
View File

@ -55,7 +55,7 @@ static const struct pad_config early_gpio_table[] = {
/* PCH_WP_OD */
PAD_CFG_GPI(GPIO_190, NONE, DEEP),
/* H1_PCH_INT_ODL */
PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE,
PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, LEVEL, INVERT, TxDRxE,
DISPUPD),
/* H1_SLAVE_SPI_CLK_R */
PAD_CFG_NF(GPIO_79, NONE, DEEP, NF1),

2
src/mainboard/google/octopus/variants/fleex/gpio.c
View File

@ -92,7 +92,7 @@ static const struct pad_config early_gpio_table[] = {
/* PCH_WP_OD */
PAD_CFG_GPI(GPIO_190, NONE, DEEP),
/* H1_PCH_INT_ODL */
PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE,
PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, LEVEL, INVERT, TxDRxE,
DISPUPD),
/* H1_SLAVE_SPI_CLK_R */
PAD_CFG_NF(GPIO_79, NONE, DEEP, NF1),

2
src/mainboard/google/octopus/variants/meep/gpio.c
View File

@ -44,7 +44,7 @@ static const struct pad_config early_gpio_table[] = {
/* PCH_WP_OD */
PAD_CFG_GPI(GPIO_190, NONE, DEEP),
/* H1_PCH_INT_ODL */
PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE,
PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, LEVEL, INVERT, TxDRxE,
DISPUPD),
/* H1_SLAVE_SPI_CLK_R */
PAD_CFG_NF(GPIO_79, NONE, DEEP, NF1),

2
src/mainboard/google/octopus/variants/phaser/gpio.c
View File

@ -72,7 +72,7 @@ static const struct pad_config early_gpio_table[] = {
/* PCH_WP_OD */
PAD_CFG_GPI(GPIO_190, NONE, DEEP),
/* H1_PCH_INT_ODL */
PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE,
PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, LEVEL, INVERT, TxDRxE,
DISPUPD),
/* H1_SLAVE_SPI_CLK_R */
PAD_CFG_NF(GPIO_79, NONE, DEEP, NF1),