soc/intel/common: Add Intel PCIe common code
Add PCIe code support under soc/intel/common/block to initialize PCIe controller, allocate resources and configure L1 substate latency. Change-Id: I0c374317a3fe0be0bb1c5d9b16fcbc5cad83ca42 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/19665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
This commit is contained in:
Aamir Bohra
Aaron Durbin
parent
4bbfe57959
commit
2d689f9e0d
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config SOC_INTEL_COMMON_BLOCK_PCIE
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bool
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help
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Intel Processor common PCIE support
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config PCIE_DEBUG_INFO
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bool
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help
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Enable debug logs in PCIe module. Allows debug information on memory
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base and limit, prefetchable memory base and limit, prefetchable memory
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base upper 32 bits and prefetchable memory limit upper 32 bits.
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ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE) += pcie.c
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <device/pci.h>
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#include <device/pciexp.h>
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#include <device/pci_def.h>
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#include <device/pci_ids.h>
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#define CACHE_LINE_SIZE 0x10
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/* Latency tolerance reporting, max non-snoop latency value 3.14ms */
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#define PCIE_LTR_MAX_NO_SNOOP_LATENCY_VALUE 0x1003
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/* Latency tolerance reporting, max snoop latency value 3.14ms */
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#define PCIE_LTR_MAX_SNOOP_LATENCY_VALUE 0x1003
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static void pch_pcie_init(struct device *dev)
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{
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u16 reg16;
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printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n");
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/* Enable SERR */
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pci_or_config32(dev, PCI_COMMAND, PCI_COMMAND_SERR);
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/* Enable Bus Master */
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pci_or_config32(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
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/* Set Cache Line Size to 0x10 */
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pci_write_config8(dev, PCI_CACHE_LINE_SIZE, CACHE_LINE_SIZE);
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/* disable parity error response, enable ISA */
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pci_update_config16(dev, PCI_BRIDGE_CONTROL, ~1, 1<<2);
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if (IS_ENABLED(CONFIG_PCIE_DEBUG_INFO)) {
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printk(BIOS_SPEW, " MBL = 0x%08x\n",
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pci_read_config32(dev, PCI_MEMORY_BASE));
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printk(BIOS_SPEW, " PMBL = 0x%08x\n",
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pci_read_config32(dev, PCI_PREF_MEMORY_BASE));
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printk(BIOS_SPEW, " PMBU32 = 0x%08x\n",
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pci_read_config32(dev, PCI_PREF_BASE_UPPER32));
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printk(BIOS_SPEW, " PMLU32 = 0x%08x\n",
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pci_read_config32(dev, PCI_PREF_LIMIT_UPPER32));
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}
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/* Clear errors in status registers */
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reg16 = pci_read_config16(dev, PCI_STATUS);
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pci_write_config16(dev, PCI_STATUS, reg16);
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reg16 = pci_read_config16(dev, PCI_SEC_STATUS);
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pci_write_config16(dev, PCI_SEC_STATUS, reg16);
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}
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static void pcie_set_L1_ss_max_latency(device_t dev, unsigned int offset)
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{
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/* Set max snoop and non-snoop latency for the SOC */
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pci_write_config32(dev, offset,
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PCIE_LTR_MAX_NO_SNOOP_LATENCY_VALUE << 16 |
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PCIE_LTR_MAX_SNOOP_LATENCY_VALUE);
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}
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static struct pci_operations pcie_ops = {
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.set_L1_ss_latency = pcie_set_L1_ss_max_latency,
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};
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static struct device_operations device_ops = {
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.read_resources = pci_bus_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_bus_enable_resources,
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.init = pch_pcie_init,
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.scan_bus = pciexp_scan_bridge,
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.ops_pci = &pcie_ops,
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};
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static const unsigned short pcie_device_ids[] = {
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PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1,
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PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP2,
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PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP3,
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PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP4,
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PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP5,
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PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP6,
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PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP7,
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PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP8,
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PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP9,
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PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP10,
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PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP11,
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PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP12,
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PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP1,
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PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP2,
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PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP3,
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PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP4,
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PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP5,
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PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP6,
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PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP7,
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PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP8,
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PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP9,
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PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP10,
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PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP11,
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PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP12,
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PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP13,
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PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP14,
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PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP15,
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PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP16,
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PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP17,
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PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP18,
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PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP19,
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PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP20,
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PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP1,
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PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP2,
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PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP3,
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PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP4,
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PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP5,
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PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP6,
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PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP7,
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PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP8,
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PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP9,
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PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP10,
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PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP11,
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PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP12,
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PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP13,
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PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP14,
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PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP15,
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PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP16,
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PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP17,
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PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP18,
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PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP19,
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PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP20,
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PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP21,
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PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP22,
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PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP23,
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PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP24,
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0
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};
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static const struct pci_driver pch_pcie __pci_driver = {
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.ops = &device_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.devices = pcie_device_ids,
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};
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