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amd/stoneyridge: Add northbridge register macros 

Add helpers for determining the D18F1 offset for MMIO base and limit,
and I/O base/limit registers.

Change-Id: I3f61bff00b8f3ada3e1bbfb163e1f223708bd47d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Marshall Dawson 2017-11-02 16:55:44 -06:00 committed by Aaron Durbin
parent b838256a51
commit 2d69d75749
1 changed files with 19 additions and 0 deletions
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19
src/soc/amd/stoneyridge/include/soc/northbridge.h
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@ -26,15 +26,34 @@
# define CPU_CNT_MASK 0x1f /* CpuCnt + 1 = no. CPUs */
/* D18F1 - Address Map Registers */
/* MMIO base and limit */
#define D18F1_MMIO_BASE0_LO 0x80
# define MMIO_WE (1 << 1)
# define MMIO_RE (1 << 0)
#define D18F1_MMIO_LIMIT0_LO 0x84
# define MMIO_NP (1 << 7)
#define D18F1_MMIO_BASELIM0_HI 0x180
#define D18F1_MMIO_BASE8_LO 0x1a0
#define D18F1_MMIO_LIMIT8_LO 0x1a4
#define D18F1_MMIO_BASELIM8_HI 0x1c0
#define NB_MMIO_BASE_LO(reg) ((reg) * 2 * sizeof(uint32_t) + (((reg) < 8) \
? D18F1_MMIO_BASE0_LO \
: D18F1_MMIO_BASE8_LO \
- 8 * sizeof(uint64_t)))
#define NB_MMIO_LIMIT_LO(reg) (NB_MMIO_BASE_LO(reg) + sizeof(uint32_t))
#define NB_MMIO_BASELIM_HI(reg) ((reg) * sizeof(uint32_t) + (((reg) < 8) \
? D18F1_MMIO_BASELIM0_HI \
: D18F1_MMIO_BASELIM8_HI \
- 8 * sizeof(uint32_t)))
/* I/O base and limit */
#define D18F1_IO_BASE0 0xc0
# define IO_WE (1 << 1)
# define IO_RE (1 << 0)
#define D18F1_IO_LIMIT0 0xc4
#define NB_IO_BASE(reg) ((reg) * 2 * sizeof(uint32_t) + D18F1_IO_BASE0)
#define NB_IO_LIMIT(reg) (NB_IO_BASE(reg) + sizeof(uint32_t))
#define D18F1_DRAM_HOLE 0xf0
# define DRAM_HOIST_VALID (1 << 1)
# define DRAM_HOLE_VALID (1 << 0)