google/kahlee: Start Kahlee mainboard
Copied from amd/gardenia. Update the appropriate board name strings. Uses the soc/ structure. Change-Id: Ia68b16969518f4d63d5d2dea7658a472b2daca05 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Marc Jones
Martin Roth
parent
b14e04bd7c
commit
2d79f16dc8
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@ -0,0 +1,78 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015-2016 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <AGESA.h>
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#include <BiosCallOuts.h>
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#include <FchPlatform.h>
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#include <soc/imc.h>
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#include <soc/hudson.h>
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#include <stdlib.h>
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static AGESA_STATUS fch_initenv(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
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{
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AMD_CONFIG_PARAMS *StdHeader = ConfigPtr;
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if (StdHeader->Func == AMD_INIT_ENV) {
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FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData;
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printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
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if (IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM))
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oem_fan_control(FchParams_env);
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/* XHCI configuration */
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if (IS_ENABLED(CONFIG_STONEYRIDGE_XHCI_ENABLE))
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FchParams_env->Usb.Xhci0Enable = TRUE;
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else
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FchParams_env->Usb.Xhci0Enable = FALSE;
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FchParams_env->Usb.Xhci1Enable = FALSE;
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/* 8: If USB3 port is unremoveable. */
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FchParams_env->Usb.USB30PortInit = 8;
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/* SATA configuration */
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FchParams_env->Sata.SataClass = CONFIG_STONEYRIDGE_SATA_MODE;
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switch ((SATA_CLASS)CONFIG_STONEYRIDGE_SATA_MODE) {
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case SataRaid:
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case SataAhci:
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case SataAhci7804:
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case SataLegacyIde:
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FchParams_env->Sata.SataIdeMode = FALSE;
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break;
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case SataIde2Ahci:
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case SataIde2Ahci7804:
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default: /* SataNativeIde */
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FchParams_env->Sata.SataIdeMode = TRUE;
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break;
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}
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printk(BIOS_DEBUG, "Done\n");
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}
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return AGESA_SUCCESS;
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}
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const BIOS_CALLOUT_STRUCT BiosCallouts[] = {
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{AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer },
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{AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer },
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{AGESA_LOCATE_BUFFER, agesa_LocateBuffer },
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{AGESA_READ_SPD, agesa_ReadSpd },
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{AGESA_DO_RESET, agesa_Reset },
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{AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
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{AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
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{AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData },
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{AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
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{AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
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{AGESA_FCH_OEM_CALLOUT, fch_initenv },
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{AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage }
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};
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const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
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@ -0,0 +1,53 @@
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#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2015 Advanced Micro Devices, Inc.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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if BOARD_GOOGLE_KAHLEE
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select SOC_AMD_STONEYRIDGE_FP4
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select HAVE_OPTION_TABLE
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select HAVE_PIRQ_TABLE
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select HAVE_MP_TABLE
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select HAVE_ACPI_TABLES
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select BOARD_ROMSIZE_KB_8192
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select GFXUMA
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select STONEYRIDGE_IMC_FWM
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config MAINBOARD_DIR
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string
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default google/kahlee
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config MAINBOARD_PART_NUMBER
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string
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default "Kahlee"
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config MAX_CPUS
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int
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default 4
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config IRQ_SLOT_COUNT
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int
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default 11
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config ONBOARD_VGA_IS_PRIMARY
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bool
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default y
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config STONEYRIDGE_LEGACY_FREE
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bool
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default y
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endif # BOARD_GOOGLE_KAHLEE
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@ -0,0 +1,2 @@
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config BOARD_GOOGLE_KAHLEE
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bool "Kahlee"
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@ -0,0 +1,24 @@
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#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2015 Advanced Micro Devices, Inc.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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bootblock-y += bootblock/BiosCallOuts.c
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bootblock-y += bootblock/OemCustomize.c
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romstage-y += BiosCallOuts.c
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romstage-y += OemCustomize.c
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ramstage-y += BiosCallOuts.c
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ramstage-y += OemCustomize.c
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ramstage-$(CONFIG_STONEYRIDGE_IMC_FWM) += fchec.c
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@ -0,0 +1,39 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015-2016 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <agesawrapper.h>
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#include <PlatformMemoryConfiguration.h>
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#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
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static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = {
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DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY),
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NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
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NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2),
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MOTHER_BOARD_LAYERS(LAYERS_6),
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MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL,
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0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
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CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
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ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
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CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL,
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0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
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PSO_END
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};
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void OemPostParams(AMD_POST_PARAMS *PostParams)
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{
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PostParams->MemConfig.PlatformMemoryConfiguration =
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(PSO_ENTRY *)DDR4PlatformMemoryConfiguration;
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}
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@ -0,0 +1,110 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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//BTDC Due to IMC Fan, ACPI control codes
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OperationRegion(IMIO, SystemIO, 0x3E, 0x02)
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Field(IMIO , ByteAcc, NoLock, Preserve) {
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IMCX,8,
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IMCA,8
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}
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IndexField(IMCX, IMCA, ByteAcc, NoLock, Preserve) {
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Offset(0x80),
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MSTI, 8,
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MITS, 8,
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MRG0, 8,
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MRG1, 8,
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MRG2, 8,
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MRG3, 8,
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}
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Method(WACK, 0)
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{
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Store(0, Local0)
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While (LNotEqual(Local0, 0xFA)) {
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Store(MRG0, Local0)
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Sleep(10)
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}
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}
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//Init
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Method (ITZE, 0)
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{
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Store(0, MRG0)
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Store(0xB5, MRG1)
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Store(0, MRG2)
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Store(0x96, MSTI)
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WACK()
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Store(0, MRG0)
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Store(0, MRG1)
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Store(0, MRG2)
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Store(0x80, MSTI)
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WACK()
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Or(MRG2, 0x01, Local0)
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Store(0, MRG0)
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Store(0, MRG1)
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Store(Local0, MRG2)
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Store(0x81, MSTI)
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WACK()
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}
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//Sleep
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Method (IMSP, 0)
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{
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Store(0, MRG0)
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Store(0xB5, MRG1)
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Store(0, MRG2)
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Store(0x96, MSTI)
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WACK()
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Store(0, MRG0)
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Store(1, MRG1)
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Store(0, MRG2)
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Store(0x98, MSTI)
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WACK()
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Store(0, MRG0)
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Store(0xB4, MRG1)
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Store(0, MRG2)
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Store(0x96, MSTI)
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WACK()
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}
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//Wake
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Method (IMWK, 0)
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{
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Store(0, MRG0)
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Store(0xB5, MRG1)
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Store(0, MRG2)
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Store(0x96, MSTI)
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WACK()
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Store(0, MRG0)
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Store(0, MRG1)
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Store(0, MRG2)
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Store(0x80, MSTI)
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WACK()
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Or(MRG2, 0x01, Local0)
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Store(0, MRG0)
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Store(0, MRG1)
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Store(Local0, MRG2)
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Store(0x81, MSTI)
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WACK()
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}
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@ -0,0 +1,119 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015-2016 Advanced Micro Devices, Inc.
|
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*
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU General Public License for more details.
|
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*/
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Device(AAHB) {
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Name(_HID,"AAHB0000")
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Name(_UID,0x0)
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Name(_CRS, ResourceTemplate()
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{
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IRQ(Edge, ActiveHigh, Exclusive) {7}
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Memory32Fixed(ReadWrite, 0xFEDC0000, 0x2000)
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})
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Method (_STA, 0x0, NotSerialized) {
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Return (0x0F)
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}
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}
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|
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Device(GPIO) {
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Name (_HID, "AMD0030")
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Name (_CID, "AMD0030")
|
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Name(_UID, 0)
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Name(_CRS, ResourceTemplate() {
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Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {7}
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Memory32Fixed(ReadWrite, 0xFED81500, 0x300)
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})
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||||
|
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Method (_STA, 0x0, NotSerialized) {
|
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Return (0x0F)
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}
|
||||
}
|
||||
|
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Device(FUR0) {
|
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Name(_HID,"AMD0020")
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Name(_UID,0x0)
|
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Name(_CRS, ResourceTemplate() {
|
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IRQ(Edge, ActiveHigh, Exclusive) {10}
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Memory32Fixed(ReadWrite, 0xFEDC6000, 0x2000)
|
||||
})
|
||||
Method (_STA, 0x0, NotSerialized) {
|
||||
Return (0x0F)
|
||||
}
|
||||
}
|
||||
|
||||
Device(FUR1) {
|
||||
Name(_HID,"AMD0020")
|
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Name(_UID,0x1)
|
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Name(_CRS, ResourceTemplate() {
|
||||
IRQ(Edge, ActiveHigh, Exclusive) {11}
|
||||
Memory32Fixed(ReadWrite, 0xFEDC8000, 0x2000)
|
||||
})
|
||||
Method (_STA, 0x0, NotSerialized) {
|
||||
Return (0x0F)
|
||||
}
|
||||
}
|
||||
|
||||
Device(I2CA) {
|
||||
Name(_HID,"AMD0010")
|
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Name(_UID,0x0)
|
||||
Name(_CRS, ResourceTemplate() {
|
||||
IRQ(Edge, ActiveHigh, Exclusive) {3}
|
||||
Memory32Fixed(ReadWrite, 0xFEDC2000, 0x1000)
|
||||
})
|
||||
|
||||
Method (_STA, 0x0, NotSerialized) {
|
||||
Return (0x0F)
|
||||
}
|
||||
}
|
||||
|
||||
Device(I2CB)
|
||||
{
|
||||
Name(_HID,"AMD0010")
|
||||
Name(_UID,0x1)
|
||||
Name(_CRS, ResourceTemplate() {
|
||||
IRQ(Edge, ActiveHigh, Exclusive) {15}
|
||||
Memory32Fixed(ReadWrite, 0xFEDC3000, 0x1000)
|
||||
})
|
||||
Method (_STA, 0x0, NotSerialized) {
|
||||
Return (0x0F)
|
||||
}
|
||||
}
|
||||
|
||||
Device(I2CC) {
|
||||
Name(_HID,"AMD0010")
|
||||
Name(_UID,0x0)
|
||||
Name(_CRS, ResourceTemplate() {
|
||||
IRQ(Edge, ActiveHigh, Exclusive) {6}
|
||||
Memory32Fixed(ReadWrite, 0xFEDC4000, 0x1000)
|
||||
})
|
||||
|
||||
Method (_STA, 0x0, NotSerialized) {
|
||||
Return (0x0F)
|
||||
}
|
||||
}
|
||||
|
||||
Device(I2CD)
|
||||
{
|
||||
Name(_HID,"AMD0010")
|
||||
Name(_UID,0x1)
|
||||
Name(_CRS, ResourceTemplate() {
|
||||
IRQ(Edge, ActiveHigh, Exclusive) {14}
|
||||
Memory32Fixed(ReadWrite, 0xFEDC5000, 0x1000)
|
||||
})
|
||||
Method (_STA, 0x0, NotSerialized) {
|
||||
Return (0x0F)
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2013 Sage Electronic Engineering, LLC
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
Scope(\_GPE) { /* Start Scope GPE */
|
||||
|
||||
/* General event 3 */
|
||||
Method(_L03) {
|
||||
/* DBGO("\\_GPE\\_L00\n") */
|
||||
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
}
|
||||
|
||||
/* Legacy PM event */
|
||||
Method(_L08) {
|
||||
/* DBGO("\\_GPE\\_L08\n") */
|
||||
}
|
||||
|
||||
/* Temp warning (TWarn) event */
|
||||
Method(_L09) {
|
||||
/* DBGO("\\_GPE\\_L09\n") */
|
||||
/* Notify (\_TZ.TZ00, 0x80) */
|
||||
}
|
||||
|
||||
/* USB controller PME# */
|
||||
Method(_L0B) {
|
||||
/* DBGO("\\_GPE\\_L0B\n") */
|
||||
Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
}
|
||||
|
||||
/* ExtEvent0 SCI event */
|
||||
Method(_L10) {
|
||||
/* DBGO("\\_GPE\\_L10\n") */
|
||||
}
|
||||
|
||||
/* ExtEvent1 SCI event */
|
||||
Method(_L11) {
|
||||
/* DBGO("\\_GPE\\_L11\n") */
|
||||
}
|
||||
|
||||
/* GPIO0 or GEvent8 event */
|
||||
Method(_L18) {
|
||||
/* DBGO("\\_GPE\\_L18\n") */
|
||||
Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
}
|
||||
|
||||
/* Azalia SCI event */
|
||||
Method(_L1B) {
|
||||
/* DBGO("\\_GPE\\_L1B\n") */
|
||||
Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
}
|
||||
} /* End Scope GPE */
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2013 Sage Electronic Engineering, LLC
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/* Memory related values */
|
||||
Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
|
||||
Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
|
||||
Name(PBLN, 0x0) /* Length of BIOS area */
|
||||
|
||||
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
|
||||
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
|
||||
Name(HPBA, 0xFED00000) /* Base address of HPET table */
|
||||
|
||||
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
|
||||
|
||||
/* Some global data */
|
||||
Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
|
||||
Name(OSV, Ones) /* Assume nothing */
|
||||
Name(PMOD, One) /* Assume APIC */
|
||||
|
|
@ -0,0 +1,165 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015, 2016 Advanced Micro Devices, Inc.
|
||||
* Copyright (C) 2013 Sage Electronic Engineering, LLC
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/*
|
||||
DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
|
||||
)
|
||||
{
|
||||
#include "routing.asl"
|
||||
}
|
||||
*/
|
||||
|
||||
/* Routing is in System Bus scope */
|
||||
Name(PR0, Package(){
|
||||
/* NB devices */
|
||||
/* Bus 0, Dev 0 - F15 Host Controller */
|
||||
|
||||
/* Bus 0, Dev 1, Func 0 - PCI Bridge for Internal Graphics(IGP) */
|
||||
/* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */
|
||||
Package(){0x0001FFFF, 0, INTB, 0 },
|
||||
Package(){0x0001FFFF, 1, INTC, 0 },
|
||||
|
||||
|
||||
/* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */
|
||||
Package(){0x0002FFFF, 0, INTC, 0 },
|
||||
Package(){0x0002FFFF, 1, INTD, 0 },
|
||||
Package(){0x0002FFFF, 2, INTA, 0 },
|
||||
Package(){0x0002FFFF, 3, INTB, 0 },
|
||||
|
||||
/* FCH devices */
|
||||
/* Bus 0, Dev 20 - F0:SMBus/ACPI;F3:LPC;F7:SD */
|
||||
Package(){0x0014FFFF, 0, INTA, 0 },
|
||||
Package(){0x0014FFFF, 1, INTB, 0 },
|
||||
Package(){0x0014FFFF, 2, INTC, 0 },
|
||||
Package(){0x0014FFFF, 3, INTD, 0 },
|
||||
|
||||
/* Bus 0, Dev 18 Func 0 - USB: EHCI */
|
||||
Package(){0x0012FFFF, 0, INTC, 0 },
|
||||
Package(){0x0012FFFF, 1, INTB, 0 },
|
||||
|
||||
/* Bus 0, Dev 10 Func 0 - USB: xHCI */
|
||||
Package(){0x0010FFFF, 0, INTC, 0 },
|
||||
Package(){0x0010FFFF, 1, INTB, 0 },
|
||||
|
||||
/* Bus 0, Dev 17 - SATA controller */
|
||||
Package(){0x0011FFFF, 0, INTD, 0 },
|
||||
|
||||
})
|
||||
|
||||
Name(APR0, Package(){
|
||||
/* NB devices in APIC mode */
|
||||
/* Bus 0, Dev 0 - F15 Host Controller */
|
||||
|
||||
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
|
||||
Package(){0x0001FFFF, 0, 0, 43 },
|
||||
Package(){0x0001FFFF, 1, 0, 40 },
|
||||
|
||||
/* Bus 0, Dev 2 - PCIe Bridges */
|
||||
Package(){0x0002FFFF, 0, 0, 44 },
|
||||
Package(){0x0002FFFF, 1, 0, 45 },
|
||||
Package(){0x0002FFFF, 2, 0, 46 },
|
||||
Package(){0x0002FFFF, 3, 0, 47 },
|
||||
|
||||
/* SB devices in APIC mode */
|
||||
/* Bus 0, Dev 20 - F0:SMBus/ACPI;F3:LPC;F7:SD */
|
||||
Package(){0x0014FFFF, 0, 0, 16 },
|
||||
Package(){0x0014FFFF, 1, 0, 17 },
|
||||
Package(){0x0014FFFF, 2, 0, 18 },
|
||||
Package(){0x0014FFFF, 3, 0, 19 },
|
||||
|
||||
/* Bus 0, Dev 18 Func 0 - USB: EHCI */
|
||||
Package(){0x0012FFFF, 0, 0, 18 },
|
||||
Package(){0x0012FFFF, 1, 0, 17 },
|
||||
|
||||
/* Bus 0, Dev 10 Func 0 - USB: xHCI */
|
||||
Package(){0x0010FFFF, 0, 0, 18},
|
||||
Package(){0x0010FFFF, 1, 0, 17},
|
||||
|
||||
/* Bus 0, Dev 17 - SATA controller */
|
||||
Package(){0x0011FFFF, 0, 0, 19 },
|
||||
})
|
||||
|
||||
|
||||
/* GPP 0 */
|
||||
Name(PS4, Package(){
|
||||
Package(){0x0000FFFF, 0, INTA, 0 },
|
||||
Package(){0x0000FFFF, 1, INTB, 0 },
|
||||
Package(){0x0000FFFF, 2, INTC, 0 },
|
||||
Package(){0x0000FFFF, 3, INTD, 0 },
|
||||
})
|
||||
Name(APS4, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 4 */
|
||||
Package(){0x0000FFFF, 0, 0, 24 },
|
||||
Package(){0x0000FFFF, 1, 0, 25 },
|
||||
Package(){0x0000FFFF, 2, 0, 26 },
|
||||
Package(){0x0000FFFF, 3, 0, 27 },
|
||||
})
|
||||
|
||||
/* GPP 1 */
|
||||
Name(PS5, Package(){
|
||||
Package(){0x0000FFFF, 0, INTB, 0 },
|
||||
Package(){0x0000FFFF, 1, INTC, 0 },
|
||||
Package(){0x0000FFFF, 2, INTD, 0 },
|
||||
Package(){0x0000FFFF, 3, INTA, 0 },
|
||||
})
|
||||
Name(APS5, Package(){
|
||||
Package(){0x0000FFFF, 0, 0, 28 },
|
||||
Package(){0x0000FFFF, 1, 0, 29 },
|
||||
Package(){0x0000FFFF, 2, 0, 30 },
|
||||
Package(){0x0000FFFF, 3, 0, 31 },
|
||||
})
|
||||
|
||||
/* GPP 2 */
|
||||
Name(PS6, Package(){
|
||||
Package(){0x0000FFFF, 0, INTC, 0 },
|
||||
Package(){0x0000FFFF, 1, INTD, 0 },
|
||||
Package(){0x0000FFFF, 2, INTA, 0 },
|
||||
Package(){0x0000FFFF, 3, INTB, 0 },
|
||||
})
|
||||
Name(APS6, Package(){
|
||||
Package(){0x0000FFFF, 0, 0, 32 },
|
||||
Package(){0x0000FFFF, 1, 0, 33 },
|
||||
Package(){0x0000FFFF, 2, 0, 34 },
|
||||
Package(){0x0000FFFF, 3, 0, 35 },
|
||||
})
|
||||
|
||||
/* GPP 3 */
|
||||
Name(PS7, Package(){
|
||||
Package(){0x0000FFFF, 0, INTD, 0 },
|
||||
Package(){0x0000FFFF, 1, INTA, 0 },
|
||||
Package(){0x0000FFFF, 2, INTB, 0 },
|
||||
Package(){0x0000FFFF, 3, INTC, 0 },
|
||||
})
|
||||
Name(APS7, Package(){
|
||||
Package(){0x0000FFFF, 0, 0, 36 },
|
||||
Package(){0x0000FFFF, 1, 0, 37 },
|
||||
Package(){0x0000FFFF, 2, 0, 38 },
|
||||
Package(){0x0000FFFF, 3, 0, 39 },
|
||||
})
|
||||
|
||||
/* GPP 4 */
|
||||
Name(PS8, Package(){
|
||||
Package(){0x0000FFFF, 0, INTA, 0 },
|
||||
Package(){0x0000FFFF, 1, INTB, 0 },
|
||||
Package(){0x0000FFFF, 2, INTC, 0 },
|
||||
Package(){0x0000FFFF, 3, INTD, 0 },
|
||||
})
|
||||
Name(APS8, Package(){
|
||||
Package(){0x0000FFFF, 0, 0, 40 },
|
||||
Package(){0x0000FFFF, 1, 0, 41 },
|
||||
Package(){0x0000FFFF, 2, 0, 42 },
|
||||
Package(){0x0000FFFF, 3, 0, 43 },
|
||||
})
|
||||
|
|
@ -0,0 +1,86 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2013 Sage Electronic Engineering, LLC
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/* Wake status package */
|
||||
Name(WKST,Package(){Zero, Zero})
|
||||
|
||||
/*
|
||||
* \_PTS - Prepare to Sleep method
|
||||
*
|
||||
* Entry:
|
||||
* Arg0=The value of the sleeping state S1=1, S2=2, etc
|
||||
*
|
||||
* Exit:
|
||||
* -none-
|
||||
*
|
||||
* The _PTS control method is executed at the beginning of the sleep process
|
||||
* for S1-S5. The sleeping value is passed to the _PTS control method. This
|
||||
* control method may be executed a relatively long time before entering the
|
||||
* sleep state and the OS may abort the operation without notification to
|
||||
* the ACPI driver. This method cannot modify the configuration or power
|
||||
* state of any device in the system.
|
||||
*/
|
||||
Method(_PTS, 1) {
|
||||
/* DBGO("\\_PTS\n") */
|
||||
/* DBGO("From S0 to S") */
|
||||
/* DBGO(Arg0) */
|
||||
/* DBGO("\n") */
|
||||
|
||||
/* Clear wake status structure. */
|
||||
Store(0, PEWD)
|
||||
Store(0, Index(WKST,0))
|
||||
Store(0, Index(WKST,1))
|
||||
Store(7, UPWS)
|
||||
} /* End Method(\_PTS) */
|
||||
|
||||
/*
|
||||
* \_BFS OEM Back From Sleep method
|
||||
*
|
||||
* Entry:
|
||||
* Arg0=The value of the sleeping state S1=1, S2=2
|
||||
*
|
||||
* Exit:
|
||||
* -none-
|
||||
*/
|
||||
Method(\_BFS, 1) {
|
||||
/* DBGO("\\_BFS\n") */
|
||||
/* DBGO("From S") */
|
||||
/* DBGO(Arg0) */
|
||||
/* DBGO(" to S0\n") */
|
||||
}
|
||||
|
||||
/*
|
||||
* \_WAK System Wake method
|
||||
*
|
||||
* Entry:
|
||||
* Arg0=The value of the sleeping state S1=1, S2=2
|
||||
*
|
||||
* Exit:
|
||||
* Return package of 2 DWords
|
||||
* Dword 1 - Status
|
||||
* 0x00000000 wake succeeded
|
||||
* 0x00000001 Wake was signaled but failed due to lack of power
|
||||
* 0x00000002 Wake was signaled but failed due to thermal condition
|
||||
* Dword 2 - Power Supply state
|
||||
* if non-zero the effective S-state the power supply entered
|
||||
*/
|
||||
Method(\_WAK, 1) {
|
||||
/* DBGO("\\_WAK\n") */
|
||||
/* DBGO("From S") */
|
||||
/* DBGO(Arg0) */
|
||||
/* DBGO(" to S0\n") */
|
||||
|
||||
Return(WKST)
|
||||
} /* End Method(\_WAK) */
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 Advanced Micro Devices, Inc.
|
||||
* Copyright (C) 2013 Sage Electronic Engineering, LLC
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/* simple name description */
|
||||
/*
|
||||
DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
|
||||
)
|
||||
{
|
||||
#include "usb.asl"
|
||||
}
|
||||
*/
|
||||
|
||||
/* USB overcurrent mapping pins. */
|
||||
Name(UOM0, 0)
|
||||
Name(UOM1, 2)
|
||||
Name(UOM2, 0)
|
||||
Name(UOM3, 7)
|
||||
Name(UOM4, 2)
|
||||
Name(UOM5, 2)
|
||||
Name(UOM6, 6)
|
||||
Name(UOM7, 2)
|
||||
Name(UOM8, 6)
|
||||
Name(UOM9, 6)
|
||||
|
||||
/* USB Overcurrent GPEs */
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <agesawrapper.h>
|
||||
|
||||
#include <console/console.h>
|
||||
#include <string.h>
|
||||
#include <arch/acpi.h>
|
||||
#include <arch/acpigen.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cpu/amd/mtrr.h>
|
||||
#include <cpu/amd/amdfam16.h>
|
||||
|
||||
#define IO_APIC2_ADDR 0xFEC20000
|
||||
|
||||
unsigned long acpi_fill_madt(unsigned long current)
|
||||
{
|
||||
/* create all subtables for processors */
|
||||
current = acpi_create_madt_lapics(current);
|
||||
|
||||
/* Write Kern IOAPIC, only one */
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current,
|
||||
CONFIG_MAX_CPUS, IO_APIC_ADDR, 0);
|
||||
|
||||
/* TODO: Remove the hardcode */
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current,
|
||||
CONFIG_MAX_CPUS+1, IO_APIC2_ADDR, 24);
|
||||
|
||||
current += acpi_create_madt_irqoverride(
|
||||
(acpi_madt_irqoverride_t *)current, 0, 0, 2, 0);
|
||||
current += acpi_create_madt_irqoverride(
|
||||
(acpi_madt_irqoverride_t *)current, 0, 9, 9, 0xF);
|
||||
/* 0: mean bus 0--->ISA */
|
||||
/* 0: PIC 0 */
|
||||
/* 2: APIC 2 */
|
||||
/* 5 mean: 0101 --> Edge-triggered, Active high */
|
||||
|
||||
/* create all subtables for processors */
|
||||
current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current,
|
||||
0xff, 5, 1);
|
||||
/* 1: LINT1 connect to NMI */
|
||||
|
||||
return current;
|
||||
}
|
||||
|
|
@ -0,0 +1 @@
|
|||
Category: eval
|
||||
|
|
@ -0,0 +1,69 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015-2016 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <AGESA.h>
|
||||
#include <BiosCallOuts.h>
|
||||
#include <FchPlatform.h>
|
||||
#include <soc/hudson.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
static const GPIO_CONTROL oem_kahlee_gpio[] = {
|
||||
/* BT radio disable */
|
||||
{14, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
|
||||
| FCH_GPIO_OUTPUT_ENABLE},
|
||||
/* NFC PU */
|
||||
{64, Function0, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
|
||||
| FCH_GPIO_OUTPUT_ENABLE},
|
||||
/* NFC wake */
|
||||
{65, Function0, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
|
||||
| FCH_GPIO_OUTPUT_ENABLE},
|
||||
/* Webcam */
|
||||
{66, Function0, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
|
||||
| FCH_GPIO_OUTPUT_ENABLE},
|
||||
/* PCIe presence detect */
|
||||
{69, Function0, FCH_GPIO_PULL_UP_ENABLE},
|
||||
/* GPS sleep */
|
||||
{70, Function0, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
|
||||
| FCH_GPIO_OUTPUT_ENABLE},
|
||||
/* MUX for Power Express Eval */
|
||||
{116, Function1, FCH_GPIO_PULL_DOWN_ENABLE},
|
||||
/* SD power */
|
||||
{119, Function2, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
|
||||
| FCH_GPIO_OUTPUT_ENABLE},
|
||||
{-1}
|
||||
};
|
||||
|
||||
static AGESA_STATUS fch_initreset(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
|
||||
{
|
||||
AMD_CONFIG_PARAMS *StdHeader = ConfigPtr;
|
||||
|
||||
if (StdHeader->Func == AMD_INIT_RESET) {
|
||||
FCH_RESET_DATA_BLOCK *FchParams_reset;
|
||||
FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData;
|
||||
printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
|
||||
FchParams_reset->FchReset.SataEnable = hudson_sata_enable();
|
||||
FchParams_reset->FchReset.IdeEnable = hudson_ide_enable();
|
||||
FchParams_reset->EarlyOemGpioTable = oem_kahlee_gpio;
|
||||
printk(BIOS_DEBUG, "Done\n");
|
||||
}
|
||||
|
||||
return AGESA_SUCCESS;
|
||||
}
|
||||
|
||||
const BIOS_CALLOUT_STRUCT BiosCallouts[] = {
|
||||
{AGESA_FCH_OEM_CALLOUT, fch_initreset },
|
||||
};
|
||||
|
||||
const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
|
||||
|
|
@ -0,0 +1,154 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015-2016 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <agesawrapper.h>
|
||||
#include <PlatformMemoryConfiguration.h>
|
||||
|
||||
#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
|
||||
|
||||
static const PCIe_PORT_DESCRIPTOR PortList[] = {
|
||||
/* Init port descriptor (PCIe port, Lanes 7:4, D2F1) for x4 slot */
|
||||
{
|
||||
0,
|
||||
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
|
||||
PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,
|
||||
2, 1,
|
||||
HotplugDisabled,
|
||||
PcieGenMaxSupported,
|
||||
PcieGenMaxSupported,
|
||||
AspmL0sL1, 0x04, 0)
|
||||
},
|
||||
/* Initialize Port descriptor (PCIe port, Lanes 1:0, D2F2) for M.2 */
|
||||
{
|
||||
0,
|
||||
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 1),
|
||||
PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,
|
||||
2, 2,
|
||||
HotplugDisabled,
|
||||
PcieGenMaxSupported,
|
||||
PcieGenMaxSupported,
|
||||
AspmL0sL1, 0x17, 0)
|
||||
},
|
||||
/* Disable M.2 x1 on lane 1, D2F3 */
|
||||
{
|
||||
0,
|
||||
PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 1, 1),
|
||||
PCIE_PORT_DATA_INITIALIZER_V2(PortDisabled, ChannelTypeExt6db,
|
||||
2, 3,
|
||||
HotplugDisabled,
|
||||
PcieGenMaxSupported,
|
||||
PcieGenMaxSupported,
|
||||
AspmL0sL1, 0x17, 0)
|
||||
},
|
||||
/* Initialize Port descriptor (PCIe port, Lane 2, D2F4) for x1 slot */
|
||||
{
|
||||
0,
|
||||
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2),
|
||||
PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,
|
||||
2, 4,
|
||||
HotplugDisabled,
|
||||
PcieGenMaxSupported,
|
||||
PcieGenMaxSupported,
|
||||
AspmL0sL1, 0x13, 0)
|
||||
},
|
||||
/* Initialize Port descriptor (PCIe port, Lane3, D2F5) for SD */
|
||||
{
|
||||
DESCRIPTOR_TERMINATE_LIST,
|
||||
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3),
|
||||
PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,
|
||||
2, 5,
|
||||
HotplugDisabled,
|
||||
PcieGenMaxSupported,
|
||||
PcieGenMaxSupported,
|
||||
AspmL0sL1, 0x16, 0)
|
||||
},
|
||||
};
|
||||
|
||||
static const PCIe_DDI_DESCRIPTOR DdiList[] = {
|
||||
/* DDI0 - eDP */
|
||||
{
|
||||
0,
|
||||
PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
|
||||
PCIE_DDI_DATA_INITIALIZER(ConnectorTypeEDP, Aux1, Hdp1)
|
||||
},
|
||||
/* DDI1 - DP */
|
||||
{
|
||||
0,
|
||||
PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
|
||||
PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
|
||||
},
|
||||
/* DDI2 - HDMI */
|
||||
{
|
||||
DESCRIPTOR_TERMINATE_LIST,
|
||||
PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 16, 19),
|
||||
PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux3, Hdp3)
|
||||
},
|
||||
};
|
||||
|
||||
static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
|
||||
.Flags = DESCRIPTOR_TERMINATE_LIST,
|
||||
.SocketId = 0,
|
||||
.PciePortList = PortList,
|
||||
.DdiLinkList = DdiList
|
||||
};
|
||||
|
||||
static const UINT32 AzaliaCodecAlc286Table[] = {
|
||||
0x00172051, 0x001721C7, 0x00172222, 0x00172310,
|
||||
0x0017FF00, 0x0017FF00, 0x0017FF00, 0x0017FF00,
|
||||
0x01271C50, 0x01271D01, 0x01271EA6, 0x01271FB7,
|
||||
0x01371C00, 0x01371D00, 0x01371E00, 0x01371F40,
|
||||
0x01471C10, 0x01471D01, 0x01471E17, 0x01471F90,
|
||||
0x01771CF0, 0x01771D11, 0x01771E11, 0x01771F41,
|
||||
0x01871C40, 0x01871D10, 0x01871EA1, 0x01871F04,
|
||||
0x01971CF0, 0x01971D11, 0x01971E11, 0x01971F41,
|
||||
0x01A71CF0, 0x01A71D11, 0x01A71E11, 0x01A71F41,
|
||||
0x01D71C2D, 0x01D71DA5, 0x01D71E67, 0x01D71F40,
|
||||
0x01E71C30, 0x01E71D11, 0x01E71E45, 0x01E71F04,
|
||||
0x02171C20, 0x02171D10, 0x02171E21, 0x02171F04,
|
||||
0x02050071, 0x02040014, 0x02050010, 0x02040C22,
|
||||
0x0205004F, 0x0204B029, 0x0205002B, 0x02040C50,
|
||||
0x0205002D, 0x02041020, 0x02050020, 0x02040000,
|
||||
0x02050019, 0x02040817, 0x02050035, 0x02041AA5,
|
||||
0x02050063, 0x02042906, 0x02050063, 0x02042906,
|
||||
0xffffffff
|
||||
};
|
||||
|
||||
static CONST CODEC_VERB_TABLE_LIST CodecTableList[] = {
|
||||
{ 0x10ec0286, AzaliaCodecAlc286Table},
|
||||
{ 0x0FFFFFFFF, (void *)0x0FFFFFFFF}
|
||||
};
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/**
|
||||
* OemCustomizeInitEarly
|
||||
*
|
||||
* Description:
|
||||
* This is the stub function will call the host environment through the
|
||||
* binary block interface (call-out port) to provide a user hook opportunity.
|
||||
*
|
||||
* Parameters:
|
||||
* @param[in] **PeiServices
|
||||
* @param[in] *InitEarly
|
||||
*
|
||||
* @retval VOID
|
||||
*
|
||||
**/
|
||||
/*---------------------------------------------------------------------------*/
|
||||
VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly)
|
||||
{
|
||||
InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
|
||||
InitEarly->PlatformConfig.AzaliaCodecVerbTable =
|
||||
(uint64_t)(uintptr_t)CodecTableList;
|
||||
}
|
||||
|
|
@ -0,0 +1,109 @@
|
|||
#*****************************************************************************
|
||||
#
|
||||
# This file is part of the coreboot project.
|
||||
#
|
||||
# Copyright (C) 2015 Advanced Micro Devices, Inc.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; version 2 of the License.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#*****************************************************************************
|
||||
|
||||
entries
|
||||
|
||||
#start-bit length config config-ID name
|
||||
#0 8 r 0 seconds
|
||||
#8 8 r 0 alarm_seconds
|
||||
#16 8 r 0 minutes
|
||||
#24 8 r 0 alarm_minutes
|
||||
#32 8 r 0 hours
|
||||
#40 8 r 0 alarm_hours
|
||||
#48 8 r 0 day_of_week
|
||||
#56 8 r 0 day_of_month
|
||||
#64 8 r 0 month
|
||||
#72 8 r 0 year
|
||||
#80 4 r 0 rate_select
|
||||
#84 3 r 0 REF_Clock
|
||||
#87 1 r 0 UIP
|
||||
#88 1 r 0 auto_switch_DST
|
||||
#89 1 r 0 24_hour_mode
|
||||
#90 1 r 0 binary_values_enable
|
||||
#91 1 r 0 square-wave_out_enable
|
||||
#92 1 r 0 update_finished_enable
|
||||
#93 1 r 0 alarm_interrupt_enable
|
||||
#94 1 r 0 periodic_interrupt_enable
|
||||
#95 1 r 0 disable_clock_updates
|
||||
#96 288 r 0 temporary_filler
|
||||
0 384 r 0 reserved_memory
|
||||
384 1 e 4 boot_option
|
||||
386 1 e 1 ECC_memory
|
||||
388 4 h 0 reboot_counter
|
||||
392 3 e 5 baud_rate
|
||||
395 1 e 1 hw_scrubber
|
||||
396 1 e 1 interleave_chip_selects
|
||||
397 2 e 8 max_mem_clock
|
||||
399 1 e 2 multi_core
|
||||
400 1 e 1 power_on_after_fail
|
||||
412 4 e 6 debug_level
|
||||
416 4 e 7 boot_first
|
||||
420 4 e 7 boot_second
|
||||
424 4 e 7 boot_third
|
||||
428 4 h 0 boot_index
|
||||
432 8 h 0 boot_countdown
|
||||
440 4 e 9 slow_cpu
|
||||
444 1 e 1 nmi
|
||||
445 1 e 1 iommu
|
||||
728 256 h 0 user_data
|
||||
984 16 h 0 check_sum
|
||||
# Reserve the extended AMD configuration registers
|
||||
1000 24 r 0 amd_reserved
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
5 0 115200
|
||||
5 1 57600
|
||||
5 2 38400
|
||||
5 3 19200
|
||||
5 4 9600
|
||||
5 5 4800
|
||||
5 6 2400
|
||||
5 7 1200
|
||||
6 6 Notice
|
||||
6 7 Info
|
||||
6 8 Debug
|
||||
6 9 Spew
|
||||
7 0 Network
|
||||
7 1 HDD
|
||||
7 2 Floppy
|
||||
7 8 Fallback_Network
|
||||
7 9 Fallback_HDD
|
||||
7 10 Fallback_Floppy
|
||||
#7 3 ROM
|
||||
8 0 400Mhz
|
||||
8 1 333Mhz
|
||||
8 2 266Mhz
|
||||
8 3 200Mhz
|
||||
9 0 off
|
||||
9 1 87.5%
|
||||
9 2 75.0%
|
||||
9 3 62.5%
|
||||
9 4 50.0%
|
||||
9 5 37.5%
|
||||
9 6 25.0%
|
||||
9 7 12.5%
|
||||
|
||||
checksums
|
||||
|
||||
checksum 392 983 984
|
||||
|
|
@ -0,0 +1,56 @@
|
|||
#
|
||||
# This file is part of the coreboot project.
|
||||
#
|
||||
# Copyright (C) 2015-2017 Advanced Micro Devices, Inc.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; version 2 of the License.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
chip soc/amd/stoneyridge
|
||||
|
||||
register "spdAddrLookup" = "
|
||||
{
|
||||
{ {0xA2, 0x00} }, // socket 0 - Channel 0, slots 0 & 1
|
||||
}"
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 10 on end
|
||||
end
|
||||
device domain 0 on
|
||||
subsystemid 0x1022 0x1410 inherit
|
||||
device pci 0.0 on end # Root Complex
|
||||
device pci 1.0 on end # Internal Graphics P2P bridge 0x98e4
|
||||
device pci 1.1 on end # Internal Multimedia
|
||||
device pci 2.0 on end # PCIe Host Bridge
|
||||
device pci 2.1 on end # x4 PCIe slot
|
||||
device pci 2.2 on end # M.2 slot
|
||||
device pci 2.3 on end # M.2 slot
|
||||
device pci 2.4 on end # x1 PCIe slot
|
||||
device pci 2.5 on end # Cardreader
|
||||
# devices on the NB/SB Link, but on the same pci bus
|
||||
device pci 9.0 on end # PCIe Host Bridge
|
||||
device pci 9.2 on end # HDA
|
||||
device pci 10.0 on end # xHCI
|
||||
device pci 11.0 on end # SATA
|
||||
device pci 12.0 on end # EHCI
|
||||
device pci 14.0 on # SM
|
||||
chip drivers/generic/generic # dimm 0-0-0
|
||||
device i2c 51 on end
|
||||
end
|
||||
end # SM
|
||||
device pci 14.3 on end # LPC 0x790e
|
||||
device pci 14.7 on end # SD
|
||||
device pci 18.0 on end
|
||||
device pci 18.1 on end
|
||||
device pci 18.2 on end
|
||||
device pci 18.3 on end
|
||||
device pci 18.4 on end
|
||||
device pci 18.5 on end
|
||||
end #domain
|
||||
end #chip soc/amd/stoneyridge
|
||||
|
|
@ -0,0 +1,83 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/* DefinitionBlock Statement */
|
||||
DefinitionBlock (
|
||||
"DSDT.AML", /* Output filename */
|
||||
"DSDT", /* Signature */
|
||||
0x02, /* DSDT Revision, needs to be 2 for 64bit */
|
||||
"GOOGLE ", /* OEMID */
|
||||
"COREBOOT", /* TABLE ID */
|
||||
0x00010001 /* OEM Revision */
|
||||
)
|
||||
{ /* Start of ASL file */
|
||||
/* #include <arch/x86/acpi/debug.asl> */ /* as needed */
|
||||
|
||||
/* Globals for the platform */
|
||||
#include "acpi/mainboard.asl"
|
||||
|
||||
/* Describe the USB Overcurrent pins */
|
||||
#include "acpi/usb_oc.asl"
|
||||
|
||||
/* PCI IRQ mapping for the Southbridge */
|
||||
#include <pcie.asl>
|
||||
|
||||
/* Describe the processor tree (\_PR) */
|
||||
#include <cpu.asl>
|
||||
|
||||
/* Contains the supported sleep states for this chipset */
|
||||
#include <sleepstates.asl>
|
||||
|
||||
/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
|
||||
#include "acpi/sleep.asl"
|
||||
|
||||
/* System Bus */
|
||||
Scope(\_SB) { /* Start \_SB scope */
|
||||
/* global utility methods expected within the \_SB scope */
|
||||
#include <arch/x86/acpi/globutil.asl>
|
||||
|
||||
/* IRQ Routing mapping for this platform (in \_SB scope) */
|
||||
#include "acpi/routing.asl"
|
||||
|
||||
Device(PWRB) {
|
||||
Name(_HID, EISAID("PNP0C0C"))
|
||||
Name(_UID, 0xAA)
|
||||
Name(_PRW, Package () {3, 0x04})
|
||||
Name(_STA, 0x0B)
|
||||
}
|
||||
|
||||
Device(PCI0) {
|
||||
/* Describe the AMD Northbridge */
|
||||
#include <northbridge.asl>
|
||||
|
||||
/* Describe the AMD Fusion Controller Hub Southbridge */
|
||||
#include <fch.asl>
|
||||
}
|
||||
|
||||
/* Describe PCI INT[A-H] for the Southbridge */
|
||||
#include <pci_int.asl>
|
||||
|
||||
/* Describe the devices in the Southbridge */
|
||||
#include "acpi/carrizo_fch.asl"
|
||||
|
||||
} /* End \_SB scope */
|
||||
|
||||
/* Describe SMBUS for the Southbridge */
|
||||
#include <smbus.asl>
|
||||
|
||||
/* Define the General Purpose Events for the platform */
|
||||
#include "acpi/gpe.asl"
|
||||
}
|
||||
/* End of ASL file */
|
||||
|
|
@ -0,0 +1,65 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include "fchec.h"
|
||||
|
||||
void agesawrapper_fchecfancontrolservice(void)
|
||||
{
|
||||
FCH_DATA_BLOCK LateParams;
|
||||
|
||||
/* Thermal Zone Parameter */
|
||||
LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00;
|
||||
LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */
|
||||
LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d;
|
||||
LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0xc6;
|
||||
LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00;
|
||||
LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x04;
|
||||
/* SMBUS Address for SMBUS based temperature sensor */
|
||||
LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98;
|
||||
LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg7 = 0x01;
|
||||
/* PWM steping rate in unit of PWM level percentage */
|
||||
LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0x01;
|
||||
LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0x00;
|
||||
|
||||
/* IMC Fan Policy temperature thresholds */
|
||||
LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00;
|
||||
LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */
|
||||
LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x3c; /*AC0 threshold */
|
||||
LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x28; /*AC1 in oC */
|
||||
LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0xff; /*AC2 in oC */
|
||||
LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 undefined */
|
||||
LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff; /*AC4 undefined */
|
||||
LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff; /*AC5 undefined */
|
||||
LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff; /*AC6 undefined */
|
||||
LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff; /*AC7 undefined */
|
||||
LateParams.Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b; /*crit threshold */
|
||||
LateParams.Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00;
|
||||
|
||||
/* IMC Fan Policy PWM Settings */
|
||||
LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00;
|
||||
LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */
|
||||
LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0x50; /* AL0 percent */
|
||||
LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0x32; /* AL1 percent */
|
||||
LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0xff; /* AL2 percent */
|
||||
LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0xff; /* AL3 percent */
|
||||
LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0xff; /* AL4 percent */
|
||||
LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0xff; /* AL5 percent */
|
||||
LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percent */
|
||||
LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percent */
|
||||
|
||||
LateParams.Imc.EcStruct.IMCFUNSupportBitMap = 0x111;
|
||||
|
||||
FchECfancontrolservice(&LateParams);
|
||||
}
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef GOOGLE_KAHLEE_FCHEC
|
||||
#define GOOGLE_KAHLEE_FCHEC
|
||||
|
||||
#include <soc/imc.h>
|
||||
#include "Porting.h"
|
||||
#include "AGESA.h"
|
||||
#include "FchCommonCfg.h"
|
||||
|
||||
extern VOID FchECfancontrolservice (IN VOID *FchDataPtr);
|
||||
void agesawrapper_fchecfancontrolservice(void);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,101 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <arch/pirq_routing.h>
|
||||
#include <cpu/amd/amdfam16.h>
|
||||
|
||||
static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
|
||||
u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
|
||||
u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
|
||||
u8 slot, u8 rfu)
|
||||
{
|
||||
pirq_info->bus = bus;
|
||||
pirq_info->devfn = devfn;
|
||||
pirq_info->irq[0].link = link0;
|
||||
pirq_info->irq[0].bitmap = bitmap0;
|
||||
pirq_info->irq[1].link = link1;
|
||||
pirq_info->irq[1].bitmap = bitmap1;
|
||||
pirq_info->irq[2].link = link2;
|
||||
pirq_info->irq[2].bitmap = bitmap2;
|
||||
pirq_info->irq[3].link = link3;
|
||||
pirq_info->irq[3].bitmap = bitmap3;
|
||||
pirq_info->slot = slot;
|
||||
pirq_info->rfu = rfu;
|
||||
}
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
struct irq_routing_table *pirq;
|
||||
struct irq_info *pirq_info;
|
||||
u32 slot_num;
|
||||
u8 *v;
|
||||
|
||||
u8 sum = 0;
|
||||
int i;
|
||||
|
||||
/* Align the table to be 16 byte aligned. */
|
||||
addr += 15;
|
||||
addr &= ~15;
|
||||
|
||||
/* This table must be between 0xf0000 & 0x100000 */
|
||||
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
|
||||
|
||||
pirq = (void *)(addr);
|
||||
v = (u8 *) (addr);
|
||||
|
||||
pirq->signature = PIRQ_SIGNATURE;
|
||||
pirq->version = PIRQ_VERSION;
|
||||
|
||||
pirq->rtr_bus = 0;
|
||||
pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
|
||||
|
||||
pirq->exclusive_irqs = 0;
|
||||
|
||||
pirq->rtr_vendor = 0x1002;
|
||||
pirq->rtr_device = 0x4384;
|
||||
|
||||
pirq->miniport_data = 0;
|
||||
|
||||
memset(pirq->rfu, 0, sizeof(pirq->rfu));
|
||||
|
||||
pirq_info = (void *)(&pirq->checksum + 1);
|
||||
slot_num = 0;
|
||||
|
||||
/* pci bridge */
|
||||
write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
|
||||
0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
|
||||
0);
|
||||
pirq_info++;
|
||||
|
||||
slot_num++;
|
||||
|
||||
pirq->size = 32 + 16 * slot_num;
|
||||
|
||||
for (i = 0; i < pirq->size; i++)
|
||||
sum += v[i];
|
||||
|
||||
sum = pirq->checksum - sum;
|
||||
|
||||
if (sum != pirq->checksum)
|
||||
pirq->checksum = sum;
|
||||
|
||||
printk(BIOS_INFO, "write_pirq_routing_table done.\n");
|
||||
|
||||
return (unsigned long)pirq_info;
|
||||
}
|
||||
|
|
@ -0,0 +1,94 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <arch/acpi.h>
|
||||
#include <agesawrapper.h>
|
||||
#include <amd_pci_util.h>
|
||||
|
||||
/***********************************************************
|
||||
* These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
|
||||
* This table is responsible for physically routing the PIC and
|
||||
* IOAPIC IRQs to the different PCI devices on the system. It
|
||||
* is read and written via registers 0xC00/0xC01 as an
|
||||
* Index/Data pair. These values are chipset and mainboard
|
||||
* dependent and should be updated accordingly.
|
||||
*
|
||||
* These values are used by the PCI configuration space,
|
||||
* MP Tables. TODO: Make ACPI use these values too.
|
||||
*/
|
||||
const u8 mainboard_picr_data[] = {
|
||||
[0x00] = 0x03, 0x04, 0x05, 0x07, 0x0B, 0x0A, 0x1F, 0x1F,
|
||||
[0x08] = 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
|
||||
[0x10] = 0x1F, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x1F,
|
||||
[0x18] = 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
[0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00,
|
||||
[0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
[0x30] = 0x05, 0x04, 0x05, 0x04, 0x04, 0x05, 0x04, 0x05,
|
||||
[0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
[0x40] = 0x04, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
[0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
[0x50] = 0x03, 0x04, 0x05, 0x07, 0x1F, 0x1F, 0x1F, 0x1F,
|
||||
[0x58] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
|
||||
[0x60] = 0x1F, 0x1F, 0x07, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
|
||||
[0x68] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
|
||||
[0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F,
|
||||
[0x78] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
|
||||
};
|
||||
|
||||
const u8 mainboard_intr_data[] = {
|
||||
[0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
|
||||
[0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
|
||||
[0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x1F, 0x1F, 0x10,
|
||||
[0x18] = 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
[0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00,
|
||||
[0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
[0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00,
|
||||
[0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
[0x40] = 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
[0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
[0x50] = 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00,
|
||||
[0x58] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
[0x60] = 0x1F, 0x1F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
[0x68] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
[0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F,
|
||||
[0x78] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
};
|
||||
|
||||
/* PIRQ Setup */
|
||||
static void pirq_setup(void)
|
||||
{
|
||||
intr_data_ptr = mainboard_intr_data;
|
||||
picr_data_ptr = mainboard_picr_data;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*************************************************
|
||||
* enable the dedicated function in kahlee board.
|
||||
*************************************************/
|
||||
static void kahlee_enable(device_t dev)
|
||||
{
|
||||
printk(BIOS_INFO, "Mainboard "
|
||||
CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
|
||||
|
||||
/* Initialize the PIRQ data structures for consumption */
|
||||
pirq_setup();
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.enable_dev = kahlee_enable,
|
||||
};
|
||||
|
|
@ -0,0 +1,167 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <device/pci.h>
|
||||
#include <arch/io.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <cpu/amd/amdfam15.h>
|
||||
#include <arch/cpu.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <soc/hudson.h>
|
||||
#include <amd_pci_util.h>
|
||||
|
||||
static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
|
||||
{
|
||||
mc->mpc_length += length;
|
||||
mc->mpc_entry_count++;
|
||||
}
|
||||
|
||||
static void my_smp_write_bus(struct mp_config_table *mc,
|
||||
unsigned char id, const char *bustype)
|
||||
{
|
||||
struct mpc_config_bus *mpc;
|
||||
mpc = smp_next_mpc_entry(mc);
|
||||
memset(mpc, '\0', sizeof(*mpc));
|
||||
mpc->mpc_type = MP_BUS;
|
||||
mpc->mpc_busid = id;
|
||||
memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
|
||||
smp_add_mpc_entry(mc, sizeof(*mpc));
|
||||
}
|
||||
|
||||
static void *smp_write_config_table(void *v)
|
||||
{
|
||||
struct mp_config_table *mc;
|
||||
int bus_isa;
|
||||
|
||||
/*
|
||||
* By the time this function gets called, the IOAPIC registers
|
||||
* have been written so they can be read to get the correct
|
||||
* APIC ID and Version
|
||||
*/
|
||||
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LOCAL_APIC_ADDR);
|
||||
memcpy(mc->mpc_oem, "AMD ", 8);
|
||||
|
||||
smp_write_processors(mc);
|
||||
|
||||
//mptable_write_buses(mc, NULL, &bus_isa);
|
||||
my_smp_write_bus(mc, 0, "PCI ");
|
||||
my_smp_write_bus(mc, 1, "PCI ");
|
||||
bus_isa = 0x02;
|
||||
my_smp_write_bus(mc, bus_isa, "ISA ");
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
|
||||
|
||||
smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
|
||||
|
||||
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
#define IO_LOCAL_INT(type, intr, apicid, pin) \
|
||||
smp_write_lintsrc(mc, (type), \
|
||||
MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, \
|
||||
(intr), (apicid), (pin))
|
||||
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
|
||||
|
||||
/* PCI interrupts are level triggered, and are
|
||||
* associated with a specific bus/device/function tuple.
|
||||
*/
|
||||
#define PCI_INT(bus, dev, int_sign, pin) \
|
||||
smp_write_intsrc(mc, mp_INT, \
|
||||
MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), \
|
||||
(((dev)<<2)|(int_sign)), ioapic_id, (pin))
|
||||
|
||||
/* Internal VGA */
|
||||
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
|
||||
PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
|
||||
|
||||
/* SMBUS */
|
||||
PCI_INT(0x0, 0x14, 0x0, 0x10);
|
||||
|
||||
/* HD Audio */
|
||||
PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
|
||||
|
||||
/* USB */
|
||||
PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
|
||||
PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
|
||||
PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
|
||||
PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
|
||||
PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
|
||||
PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
|
||||
PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
|
||||
|
||||
/* sata */
|
||||
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
|
||||
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
|
||||
|
||||
/* on board NIC & Slot PCIE. */
|
||||
|
||||
/* PCI slots */
|
||||
device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
|
||||
if (dev && dev->enabled) {
|
||||
u8 bus_pci = dev->link_list->secondary;
|
||||
/* PCI_SLOT 0. */
|
||||
PCI_INT(bus_pci, 0x5, 0x0, 0x14);
|
||||
PCI_INT(bus_pci, 0x5, 0x1, 0x15);
|
||||
PCI_INT(bus_pci, 0x5, 0x2, 0x16);
|
||||
PCI_INT(bus_pci, 0x5, 0x3, 0x17);
|
||||
|
||||
/* PCI_SLOT 1. */
|
||||
PCI_INT(bus_pci, 0x6, 0x0, 0x15);
|
||||
PCI_INT(bus_pci, 0x6, 0x1, 0x16);
|
||||
PCI_INT(bus_pci, 0x6, 0x2, 0x17);
|
||||
PCI_INT(bus_pci, 0x6, 0x3, 0x14);
|
||||
|
||||
/* PCI_SLOT 2. */
|
||||
PCI_INT(bus_pci, 0x7, 0x0, 0x16);
|
||||
PCI_INT(bus_pci, 0x7, 0x1, 0x17);
|
||||
PCI_INT(bus_pci, 0x7, 0x2, 0x14);
|
||||
PCI_INT(bus_pci, 0x7, 0x3, 0x15);
|
||||
}
|
||||
|
||||
/* PCIe Lan*/
|
||||
PCI_INT(0x0, 0x06, 0x0, 0x13);
|
||||
|
||||
/* FCH PCIe PortA */
|
||||
PCI_INT(0x0, 0x15, 0x0, 0x10);
|
||||
/* FCH PCIe PortB */
|
||||
PCI_INT(0x0, 0x15, 0x1, 0x11);
|
||||
/* FCH PCIe PortC */
|
||||
PCI_INT(0x0, 0x15, 0x2, 0x12);
|
||||
/* FCH PCIe PortD */
|
||||
PCI_INT(0x0, 0x15, 0x3, 0x13);
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
|
||||
IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
return mptable_finalize(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr, 0);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015-2016 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
Loading…
Reference in New Issue