fix idiiot typo I did not catch.

add support for conditional enable of uarta interrupt.



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2324 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich 2006-06-18 02:28:07 +00:00
parent 48415d5cf6
commit 2d7bb59018
3 changed files with 12 additions and 1 deletions

View File

@ -124,7 +124,7 @@ dir /pc80
config chip.h
chip northbridge/amd/gx2
register "irq_map" = "0xaa5b";
register "irqmap" = "0xaa5b"
device apic_cluster 0 on
chip cpu/amd/model_gx2
device apic 0 on end
@ -136,6 +136,7 @@ chip northbridge/amd/gx2
chip southbridge/amd/cs5536
register "enable_gpio0_inta" = "1"
register "enable_ide_nand_flash" = "1"
register "enable_uarta" = "1"
device pci d.0 on end # Realtek 8139 LAN
device pci f.0 on end # ISA Bridge
device pci f.2 on end # IDE Controller

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@ -9,6 +9,7 @@ struct southbridge_amd_cs5536_config {
int lpc_irq; /* what to enable, e.g. 0x18 */
int enable_gpio0_inta; /* almost always will be true */
int enable_ide_nand_flash; /* if you are using nand flash instead of IDE drive */
int enable_uarta; /* internal uarta interrupt enable */
};
#endif /* _SOUTHBRIDGE_AMD_CS5536 */

View File

@ -97,6 +97,15 @@ static void southbridge_enable(struct device *dev)
outl(0x3081, GPIOL_INPUT_INVERT_ENABLE);
outl(GPIOL_0_SET, GPIO_MAPPER_X);
}
if (sb->enable_uarta){
printk_err("%s: enable uarta, msr MDD_IRQM_YHIGH(%x) \n",
__FUNCTION__, MDD_IRQM_YHIGH);
msr = rdmsr(MDD_IRQM_YHIGH);
msr.lo |= 0x04000000;
wrmsr(MDD_IRQM_YHIGH, msr);
}
printk_err("%s: enable_ide_nand_flash is %d\n", __FUNCTION__, sb->enable_ide_nand_flash);
if (sb->enable_ide_nand_flash) {
enable_ide_nand_flash();