GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

F15tn: Modify devicetree to fix S3 resume 

The way that devicetree.cb was configured for the family 15tn boards
was doing... interesting things to the video device initialization.
This was causing S3 resume to fail.

There is a disconnect between how the devicetree should be configured
if there are multiple HT links on the CPU and how it's configured if
there's only one HT link.  These platforms were set up as if they
had multiple HT links, which was causing duplicate instances of
devices in the device list.

The scan for the IO Hub was removed from the northbridge code which
isn't a problem for F15tn devices.

Change-Id: I3556b43027746e36b07de7cb1bece4d1b37a3c34
Signed-off-by: Martin Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/2160
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
This commit is contained in:
Martin Roth 2013-01-10 12:41:40 -07:00 committed by Martin Roth
parent b867281a07
commit 2d8815197e
3 changed files with 2 additions and 29 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/mainboard/amd/parmer/devicetree.cb
View File

@ -25,7 +25,6 @@ chip northbridge/amd/agesa/family15tn/root_complex
device pci_domain 0 on
subsystemid 0x1022 0x1410 inherit
chip northbridge/amd/agesa/family15tn # CPU side of HT root complex
device pci 18.0 on # northbridge
chip northbridge/amd/agesa/family15tn # PCI side of HT root complex
device pci 0.0 on end # Root Complex
device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
@ -38,7 +37,6 @@ chip northbridge/amd/agesa/family15tn/root_complex
device pci 7.0 on end # LAN
device pci 8.0 off end # NB/SB Link P2P bridge
end
end
chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus
device pci 10.0 on end # XHCI HC0
device pci 10.1 on end # XHCI HC1
@ -75,7 +73,7 @@ chip northbridge/amd/agesa/family15tn/root_complex
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
register "gpp_configuration" = "4"
end #southbridge/amd/hudson
# device pci 18.0 on end
device pci 18.0 on end
#device pci 18.0 on end
device pci 18.1 on end
device pci 18.2 on end

4
src/mainboard/amd/thatcher/devicetree.cb
View File

@ -25,7 +25,6 @@ chip northbridge/amd/agesa/family15tn/root_complex
device pci_domain 0 on
subsystemid 0x1022 0x1410 inherit
chip northbridge/amd/agesa/family15tn # CPU side of HT root complex
device pci 18.0 on # northbridge
chip northbridge/amd/agesa/family15tn # PCI side of HT root complex
device pci 0.0 on end # Root Complex
device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
@ -38,7 +37,6 @@ chip northbridge/amd/agesa/family15tn/root_complex
device pci 7.0 on end # LAN
device pci 8.0 off end # NB/SB Link P2P bridge
end
end
chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus
device pci 10.0 on end # XHCI HC0
device pci 10.1 on end # XHCI HC1
@ -92,7 +90,7 @@ chip northbridge/amd/agesa/family15tn/root_complex
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
register "gpp_configuration" = "4"
end #southbridge/amd/hudson
# device pci 18.0 on end
device pci 18.0 on end
#device pci 18.0 on end
device pci 18.1 on end
device pci 18.2 on end

23
src/northbridge/amd/agesa/family15tn/northbridge.c
View File

@ -446,35 +446,12 @@ static void northbridge_init(struct device *dev)
{
}
static unsigned scan_chains(device_t dev, unsigned max)
{
unsigned nodeid;
struct bus *link;
device_t io_hub = NULL;
u32 next_unitid = 0x18;
nodeid = amdfam15_nodeid(dev);
if (nodeid == 0) {
for (link = dev->link_list; link; link = link->next) {
//if (link->link_num == sblink) { /* devicetree put IO Hub on link_lsit[sblink] */
if (link->link_num == 0) { /* devicetree put IO Hub on link_lsit[0] */
io_hub = link->children;
if (!io_hub || !io_hub->enabled) {
die("I can't find the IO Hub, or IO Hub not enabled, please check the device tree.\n");
}
/* Now that nothing is overlapping it is safe to scan the children. */
max = pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7, 0);
}
}
}
return max;
}
static struct device_operations northbridge_operations = {
.read_resources = read_resources,
.set_resources = set_resources,
.enable_resources = pci_dev_enable_resources,
.init = northbridge_init,
.scan_bus = scan_chains,
.enable = 0,
.ops_pci = 0,
};