soc/intel/mtl: Change default for debug consent from 3 to 6
USB DBC is very helpful for SoC debug. TraceHub needs to be enabled in coreboot if debug consent == 2 or 4. Debug consent == 6 enables USB DBC without TraceHub enabled. This patch updates the Kconfig help text to meet PlatformDebugOption in MTL and changes debug consent to 6 in default to provide basic SoC debug capability. TEST=Boot to OS on screebo and DBC connection is OK. Change-Id: Ic12528bdd8b1feda7f1b65045c863341f932d3a2 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76880 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -345,9 +345,9 @@ config FSP_FD_PATH
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config SOC_INTEL_METEORLAKE_DEBUG_CONSENT
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int "Debug Consent for MTL"
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# USB DBC is more common for developers so make this default to 3 if
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# USB DBC is more common for developers so make this default to 6 if
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# SOC_INTEL_DEBUG_CONSENT=y
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default 3 if SOC_INTEL_DEBUG_CONSENT
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default 6 if SOC_INTEL_DEBUG_CONSENT
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default 0
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help
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This is to control debug interface on SOC.
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@ -355,9 +355,8 @@ config SOC_INTEL_METEORLAKE_DEBUG_CONSENT
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PlatformDebugConsent in FspmUpd.h has the details.
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Desired platform debug type are
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0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB),
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3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC),
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6:Enable (2-wire DCI OOB), 7:Manual
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0:Disabled, 2:Enabled Trace Active, 4:Enabled Trace Ready,
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6:Enable Trace Power-Off, 7:Manual
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config DATA_BUS_WIDTH
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int
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