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mb/google/sarien: Disable PCH Gigabit LAN 

There's no LAN connection on Arcada board, so disable PCH GBE.

BUG=N/A

Change-Id: I07c66df50dbe9fefd95a67b5af9e3f61ce6a18aa
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/30096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
This commit is contained in:
Lijian Zhao 2018-12-06 17:12:40 -08:00 committed by Patrick Georgi
parent 4cdb2b9b75
commit 2d92b1a3b1
1 changed files with 1 additions and 6 deletions
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7
src/mainboard/google/sarien/variants/arcada/devicetree.cb
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@ -78,11 +78,6 @@ chip soc/intel/cannonlake
}, },
}" }"
# PCIe port 9 for LAN
register "PcieRpEnable[8]" = "1"
register "PcieClkSrcUsage[0]" = "PCIE_CLK_LAN"
register "PcieClkSrcClkReq[0]" = "0"
# PCIe port 10 for M.2 2230 WLAN # PCIe port 10 for M.2 2230 WLAN
register "PcieRpEnable[9]" = "1" register "PcieRpEnable[9]" = "1"
register "PcieClkSrcUsage[2]" = "9" register "PcieClkSrcUsage[2]" = "9"
@ -250,6 +245,6 @@ chip soc/intel/cannonlake
device pci 1f.3 on end # Intel HDA device pci 1f.3 on end # Intel HDA
device pci 1f.4 on end # SMBus device pci 1f.4 on end # SMBus
device pci 1f.5 on end # PCH SPI device pci 1f.5 on end # PCH SPI
device pci 1f.6 on end # GbE device pci 1f.6 off end # GbE
end end
end end