diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc
index 370e017fd5..4d96edfd5f 100644
--- a/src/southbridge/intel/lynxpoint/Makefile.inc
+++ b/src/southbridge/intel/lynxpoint/Makefile.inc
@@ -30,6 +30,7 @@ ramstage-y += pci.c
 ramstage-y += pcie.c
 ramstage-y += sata.c
 ramstage-y += usb_ehci.c
+ramstage-y += usb_xhci.c
 ramstage-y += me_9.x.c
 ramstage-y += smbus.c
 ramstage-$(CONFIG_INTEL_LYNXPOINT_LP) += serialio.c
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index b01fdc04cb..6ee81d1f4b 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -224,6 +224,7 @@ void set_gpio(int gpio_num, int value);
 
 #define PCH_EHCI1_DEV		PCI_DEV(0, 0x1d, 0)
 #define PCH_EHCI2_DEV		PCI_DEV(0, 0x1a, 0)
+#define PCH_XHCI_DEV		PCI_DEV(0, 0x14, 0)
 #define PCH_ME_DEV		PCI_DEV(0, 0x16, 0)
 #define PCH_PCIE_DEV_SLOT	28
 
@@ -335,6 +336,12 @@ void set_gpio(int gpio_num, int value);
 #define SATA_IOBP_SP0G3IR	0xea000151
 #define SATA_IOBP_SP1G3IR	0xea000051
 
+/* USB Registers */
+#define EHCI_PWR_CNTL_STS	0x54
+#define  EHCI_PWR_STS_MASK	0x3
+#define  EHCI_PWR_STS_SET_D0	0x0
+#define  EHCI_PWR_STS_SET_D3	0x3
+
 /* Serial IO IOBP Registers */
 #define SIO_IOBP_PORTCTRL0	0xcb000000	/* SDIO D23:F0 */
 #define  SIO_IOBP_PORTCTRL0_ACPI_IRQ_EN		(1 << 5)
diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c
index 203a1bbfb5..add53ed5a9 100644
--- a/src/southbridge/intel/lynxpoint/smihandler.c
+++ b/src/southbridge/intel/lynxpoint/smihandler.c
@@ -20,6 +20,7 @@
  * MA 02110-1301 USA
  */
 
+#include <delay.h>
 #include <types.h>
 #include <arch/hlt.h>
 #include <arch/io.h>
@@ -105,6 +106,98 @@ static void busmaster_disable_on_bus(int bus)
         }
 }
 
+/* Handler for EHCI controller on entry to S3/S4/S5 */
+static void ehci_sleep_prepare(device_t dev, u8 slp_typ)
+{
+	u32 reg32;
+	u32 bar0_base;
+	u16 pwr_state;
+	u16 pci_cmd;
+
+	/* Check if the controller is disabled or not present */
+	bar0_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
+	if (bar0_base == 0 || bar0_base == 0xffffffff)
+		return;
+	pci_cmd = pci_read_config32(dev, PCI_COMMAND);
+
+	switch (slp_typ) {
+	case SLP_TYP_S4:
+	case SLP_TYP_S5:
+		/* Check if controller is in D3 power state */
+		pwr_state = pci_read_config16(dev, EHCI_PWR_CNTL_STS);
+		if ((pwr_state & EHCI_PWR_STS_MASK) == EHCI_PWR_STS_SET_D3) {
+			/* Put in D0 */
+			pwr_state &= ~EHCI_PWR_STS_MASK;
+			pwr_state |= EHCI_PWR_STS_SET_D0;
+			pci_write_config16(dev, EHCI_PWR_CNTL_STS, pwr_state);
+
+			/* Make sure memory bar is set */
+			pci_write_config32(dev, PCI_BASE_ADDRESS_0, bar0_base);
+
+			/* Make sure memory space is enabled */
+			pci_write_config16(dev, PCI_COMMAND, pci_cmd |
+				   PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+		}
+
+		/*
+		 * If Run/Stop (bit0) is clear in USB2.0_CMD:
+		 * - Clear Async Schedule Enable (bit5) and
+		 * - Clear Periodic Schedule Enable (bit4) and
+		 * - Set Run/Stop (bit0)
+		 */
+		reg32 = read32(bar0_base + 0x20);
+		if (reg32 & (1 << 0)) {
+			reg32 &= ~((1 << 5) | (1 << 4));
+			reg32 |= (1 << 0);
+			write32(bar0_base + 0x20, reg32);
+		}
+
+		/* Check for Port Enabled in PORTSC */
+		reg32 = read32(bar0_base + 0x64);
+		if (reg32 & (1 << 2)) {
+			/* Set suspend bit in PORTSC if not already set */
+			if (!(reg32 & (1 << 7))) {
+				reg32 |= (1 << 7);
+				write32(bar0_base + 0x64, reg32);
+			}
+
+			/* Delay 25ms !! */
+			udelay(25 * 1000);
+
+			/* Clear Run/Stop bit */
+			reg32 = read32(bar0_base + 0x20);
+			reg32 &= (1 << 0);
+			write32(bar0_base + 0x20, reg32);
+		}
+
+		pwr_state = pci_read_config16(dev, EHCI_PWR_CNTL_STS);
+		if ((pwr_state & EHCI_PWR_STS_MASK) == EHCI_PWR_STS_SET_D3) {
+			/* Restore pci command reg */
+			pci_write_config16(dev, PCI_COMMAND, pci_cmd);
+
+			/* Enable D3 */
+			pwr_state |= EHCI_PWR_STS_SET_D3;
+			pci_write_config16(dev, EHCI_PWR_CNTL_STS, pwr_state);
+		}
+	}
+}
+
+/* Handler for XHCI controller on entry to S3/S4/S5 */
+static void xhci_sleep_prepare(device_t dev, u8 slp_typ)
+{
+	u16 reg16;
+
+	switch (slp_typ) {
+	case SLP_TYP_S3:
+	case SLP_TYP_S4:
+	case SLP_TYP_S5:
+		/* Set D3Hot state and PME enable bit */
+		reg16 = pci_read_config16(dev, 0x74);
+		reg16 |= (1 << 8) | (1 << 1) | (1 << 0);
+		pci_write_config16(dev, 0x74, reg16);
+	}
+}
+
 static void southbridge_smi_sleep(void)
 {
 	u8 reg8;
@@ -132,6 +225,11 @@ static void southbridge_smi_sleep(void)
 	/* Do any mainboard sleep handling */
 	mainboard_smi_sleep(slp_typ-2);
 
+	/* USB sleep preparations */
+	ehci_sleep_prepare(PCH_EHCI1_DEV, slp_typ);
+	ehci_sleep_prepare(PCH_EHCI2_DEV, slp_typ);
+	xhci_sleep_prepare(PCH_XHCI_DEV, slp_typ);
+
 #if CONFIG_ELOG_GSMI
 	/* Log S3, S4, and S5 entry */
 	if (slp_typ >= 5)
diff --git a/src/southbridge/intel/lynxpoint/usb_ehci.c b/src/southbridge/intel/lynxpoint/usb_ehci.c
index fd7c659edd..f06151b138 100644
--- a/src/southbridge/intel/lynxpoint/usb_ehci.c
+++ b/src/southbridge/intel/lynxpoint/usb_ehci.c
@@ -26,20 +26,33 @@
 #include <usbdebug.h>
 #include <arch/io.h>
 
-static void usb_ehci_init(struct device *dev)
+static void usb_ehci_clock_gating(struct device *dev)
 {
 	u32 reg32;
 
-	/* Disable Wake on Disconnect in RMH */
-	reg32 = RCBA32(0x35b0);
-	reg32 |= 0x22;
-	RCBA32(0x35b0) = reg32;
+	/* IOBP 0xE5004001[7:6] = 11b */
+	pch_iobp_update(0xe5004001, ~0, (1 << 7)|(1 << 6));
 
+	/* Dx:F0:DCh[5,2,1] = 111b
+	 * Dx:F0:DCh[0] = 1b when EHCI controller is disabled */
+	reg32 = pci_read_config32(dev, 0xdc);
+	reg32 |= (1 << 5) | (1 << 2) | (1 << 1);
+	pci_write_config32(dev, 0xdc, reg32);
+
+	/* Dx:F0:78h[1:0] = 11b */
+	reg32 = pci_read_config32(dev, 0x78);
+	reg32 |= (1 << 1) | (1 << 0);
+	pci_write_config32(dev, 0x78, reg32);
+}
+
+static void usb_ehci_init(struct device *dev)
+{
 	printk(BIOS_DEBUG, "EHCI: Setting up controller.. ");
-	reg32 = pci_read_config32(dev, PCI_COMMAND);
-	reg32 |= PCI_COMMAND_MASTER;
-	//reg32 |= PCI_COMMAND_SERR;
-	pci_write_config32(dev, PCI_COMMAND, reg32);
+
+	usb_ehci_clock_gating(dev);
+
+	/* Disable Wake on Disconnect in RMH */
+	RCBA32_OR(0x35b0, 0x00000022);
 
 	printk(BIOS_DEBUG, "done.\n");
 }
diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c
new file mode 100644
index 0000000000..33f33f4d70
--- /dev/null
+++ b/src/southbridge/intel/lynxpoint/usb_xhci.c
@@ -0,0 +1,175 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include "pch.h"
+
+static void usb_xhci_clock_gating(device_t dev)
+{
+	u32 reg32;
+
+	/* IOBP 0xE5004001[7:6] = 11b */
+	pch_iobp_update(0xe5004001, ~0, (1 << 7)|(1 << 6));
+
+	reg32 = pci_read_config32(dev, 0x40);
+	reg32 &= ~(1 << 23); /* unsupported request */
+
+	if (pch_is_lp()) {
+		/* D20:F0:40h[18,17,8] = 111b */
+		reg32 |= (1 << 18) | (1 << 17) | (1 << 8);
+		/* D20:F0:40h[21,20,19] = 110b to enable XHCI Idle L1 */
+		reg32 &= ~(1 << 19);
+		reg32 |= (1 << 21) | (1 << 20);
+	} else {
+		/* D20:F0:40h[21,20,18,17,8] = 11111b */
+		reg32 |= (1 << 21)|(1 << 20)|(1 << 18)|(1 << 17)|(1 << 8);
+	}
+
+	/* Avoid writing upper byte as it is write-once */
+	pci_write_config16(dev, 0x40, (u16)(reg32 & 0xffff));
+	pci_write_config8(dev, 0x40 + 2, (u8)((reg32 >> 16) & 0xff));
+
+	/* D20:F0:44h[9,7,3] = 111b */
+	reg32 = pci_read_config32(dev, 0x44);
+	reg32 |= (1 << 9) | (1 << 7) | (1 << 3);
+	pci_write_config32(dev, 0x44, reg32);
+
+	reg32 = pci_read_config32(dev, 0xa0);
+	if (pch_is_lp()) {
+		/* D20:F0:A0h[18] = 1 */
+		reg32 |= (1 << 18);
+	} else {
+		/* D20:F0:A0h[6] = 1 */
+		reg32 |= (1 << 6);
+	}
+	pci_write_config32(dev, 0xa0, reg32);
+
+	/* D20:F0:A4h[13] = 0 */
+	reg32 = pci_read_config32(dev, 0xa4);
+	reg32 &= ~(1 << 13);
+	pci_write_config32(dev, 0xa4, reg32);
+}
+
+static void usb_xhci_init(device_t dev)
+{
+	struct resource *bar0 = find_resource(dev, PCI_BASE_ADDRESS_0);
+	u32 reg32;
+
+	if (!bar0 || bar0->base == 0 || bar0->base == 0xffffffff)
+		return;
+
+	/* Enable clock gating first */
+	usb_xhci_clock_gating(dev);
+
+	/* D20:F0:74h[1:0] = 11b (set D3Hot state) */
+	reg32 = pci_read_config16(dev, 0x74);
+	reg32 |= (1 << 1) | (1 << 0);
+	pci_write_config16(dev, 0x74, reg32);
+
+	reg32 = read32(bar0->base + 0x8144);
+	if (pch_is_lp()) {
+		/* XHCIBAR + 8144h[8,7,6] = 111b */
+		reg32 |= (1 << 8) | (1 << 7) | (1 << 6);
+	} else {
+		/* XHCIBAR + 8144h[8,7,6] = 100b */
+		reg32 &= ~((1 << 7) | (1 << 6));
+		reg32 |= (1 << 8);
+	}
+	write32(bar0->base + 0x8144, reg32);
+
+	if (pch_is_lp()) {
+		/* XHCIBAR + 816Ch[19:0] = 000f0038h */
+		reg32 = read32(bar0->base + 0x816c);
+		reg32 &= ~0x000fffff;
+		reg32 |= 0x000f0038;
+		write32(bar0->base + 0x816c, reg32);
+
+		/* D20:F0:B0h[17,14,13] = 100b */
+		reg32 = pci_read_config32(dev, 0xb0);
+		reg32 &= ~((1 << 14) | (1 << 13));
+		reg32 |= (1 << 17);
+		pci_write_config32(dev, 0xb0, reg32);
+
+		/* XHCIBAR + 818Ch[7:0] = FFh */
+		reg32 = read32(bar0->base + 0x818c);
+		reg32 |= 0xff;
+		write32(bar0->base + 0x818c, reg32);
+	}
+
+	reg32 = pci_read_config32(dev, 0x50);
+	if (pch_is_lp()) {
+		/* D20:F0:50h[28:0] = 0FCE2E5Fh */
+		reg32 &= ~0x1fffffff;
+		reg32 |= 0x0fce2e5f;
+	} else {
+		/* D20:F0:50h[26:0] = 07886E9Fh */
+		reg32 &= ~0x07ffffff;
+		reg32 |= 0x07886e9f;
+	}
+	pci_write_config32(dev, 0x50, reg32);
+
+	/* D20:F0:44h[31] = 1 (Access Control Bit) */
+	reg32 = pci_read_config32(dev, 0x40);
+	reg32 |= (1 << 31);
+	pci_write_config32(dev, 0x40, reg32);
+
+	/* D20:F0:40h[31,23] = 10b (OC Configuration Done) */
+	reg32 = pci_read_config32(dev, 0x40);
+	reg32 &= ~(1 << 23); /* unsupported request */
+	reg32 |= (1 << 31);
+	pci_write_config32(dev, 0x40, reg32);
+}
+
+static void usb_xhci_set_subsystem(device_t dev, unsigned vendor,
+				   unsigned device)
+{
+	if (!vendor || !device) {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				pci_read_config32(dev, PCI_VENDOR_ID));
+	} else {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				((device & 0xffff) << 16) | (vendor & 0xffff));
+	}
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = &usb_xhci_set_subsystem,
+};
+
+static struct device_operations usb_xhci_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= usb_xhci_init,
+	.ops_pci		= &lops_pci,
+};
+
+static const unsigned short pci_device_ids[] = { 0x8c31, /* LynxPoint-H */
+						 0x9c31, /* LynxPoint-LP */
+						 0 };
+
+static const struct pci_driver pch_usb_xhci __pci_driver = {
+	.ops	 = &usb_xhci_ops,
+	.vendor	 = PCI_VENDOR_ID_INTEL,
+	.devices = pci_device_ids,
+};